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Searched refs:REG_FPGA0_RF_MODE (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8188f.c474 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
476 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
502 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
504 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
552 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
560 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
562 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
565 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
568 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
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H A Drtl8xxxu_8710b.c731 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8710bu_config_channel()
733 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8710bu_config_channel()
747 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8710bu_config_channel()
749 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8710bu_config_channel()
752 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8710bu_config_channel()
755 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8710bu_config_channel()
H A Drtl8xxxu_8192f.c638 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, ht40); in rtl8192fu_config_channel()
642 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4); in rtl8192fu_config_channel()
645 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), 2); in rtl8192fu_config_channel()
656 rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK); in rtl8192fu_config_channel()
811 rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); in rtl8192f_phy_lc_calibrate()
812 rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); in rtl8192f_phy_lc_calibrate()
H A Drtl8xxxu_core.c1120 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_gen1_enable_rf()
1122 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_gen1_enable_rf()
1156 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_gen1_disable_rf()
1158 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_gen1_disable_rf()
1269 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_gen1_config_channel()
1271 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_gen1_config_channel()
1300 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_gen1_config_channel()
1302 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_gen1_config_channel()
1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8xxxu_gen2_config_channel()
1398 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8xxxu_gen2_config_channel()
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H A Drtl8xxxu_8188e.c457 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188eu_config_channel()
459 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
484 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188eu_config_channel()
486 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
H A Drtl8xxxu_regs.h868 #define REG_FPGA0_RF_MODE 0x0800 macro
H A Drtl8xxxu_8723b.c935 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE in rtl8723bu_phy_iqcalibrate()