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Searched refs:RDCSR (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/tcg/
H A Dlcsr_translate.c60 TRANS(RDCSR, gen_rdcsr, gen_helper_lcsr_rdcsr)
71 GEN_FALSE_TRANS(RDCSR)
H A Dlcsr.decode14 RDCSR 110010 ..... 00000 ..... 00100 011000 @rs_rd
/openbmc/linux/drivers/tty/
H A Dsynclink_gt.c372 #define RDCSR 0x90 /* rx DMA control/status */ macro
2116 unsigned int status = rd_reg32(info, RDCSR); in isr_rdma()
2131 wr_reg32(info, RDCSR, status); /* clear pending */ in isr_rdma()
3774 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3778 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3889 wr_reg32(info, RDCSR, BIT6); in rx_start()
3899 wr_reg32(info, RDCSR, (BIT2 + BIT0)); in rx_start()
3902 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()