Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instruc

Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instructions (Jiaxun)
- Implement Ingenic MXU ASE v1 rev2 (Siarhei)
- Enable GINVx support for I6400 and I6500 cores (Marcin)
- Generalize PCI IDE controller models (Bernhard)

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* tag 'mips-20230710' of https://github.com/philmd/qemu: (44 commits)
hw/ide/piix: Move registration of VMStateDescription to DeviceClass
hw/ide/pci: Replace some magic numbers by constants
hw/ide: Extract bmdma_status_writeb()
hw/ide: Extract IDEBus assignment into bmdma_init()
hw/isa/vt82c686: Remove via_isa_set_irq()
hw/ide/via: Wire up IDE legacy interrupts in host device
hw/ide/pci: Expose legacy interrupts as named GPIOs
target/mips: enable GINVx support for I6400 and I6500
target/mips/mxu: Add Q8SAD instruction
target/mips/mxu: Add S32SFL instruction
target/mips/mxu: Add Q8MADL instruction
target/mips/mxu: Add Q16SCOP instruction
target/mips/mxu: Add Q8MAC Q8MACSU instructions
target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions
target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions
target/mips/mxu: Add D32SLL D32SLR D32SAR instructions
target/mips/mxu: Add D32SARL D32SARW instructions
target/mips/mxu: Add S32ALN S32LUI insns
target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/mips: Implement Loongson CSR instructions

Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.

Unfortunately we don't

target/mips: Implement Loongson CSR instructions

Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.

Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while instruction encodings can be found
at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
Linux Kernel.

Our predefined CPUCFG bits are differ from actual 3A4000, since
we can't emulate all CPUCFG features present in 3A4000 for now,
we just enable bits for what we have in TCG.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com>
[JY: Fixed typo in ase_lcsr_available(),
retrict GEN_FALSE_TRANS]
[PMD: Fix meson's mips_softmmu_ss -> mips_system_ss,
restrict AddressSpace/MemoryRegion to SysEmu]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

show more ...