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Searched refs:RCC (Results 1 – 16 of 16) sorted by relevance

/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
35 The secondary index is the bit number within the RCC register bank, starting
36 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
42 drivers of the RCC IP, macros are available to generate the index in
84 The index is the bit number within the RCC registers bank, starting from RCC
H A Dst,stm32mp1.txt5 for RCC IP and on fixed clocks.
8 RCC CLOCK = st,stm32mp1-rcc-clk
11 The RCC IP is both a reset and a clock controller but this documentation only
27 with value equals to RCC clock specifier as defined in
34 with DIV coding defined in RCC associated register RCC_xxxDIVR
61 with DIV value as defined in RCC spec:
204 in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
137 The index is the bit number within the RCC registers bank, starting from RCC
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
127 The index is the bit number within the RCC registers bank, starting from RCC
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
59 The index is the bit number within the RCC registers bank, starting from RCC
/openbmc/u-boot/drivers/clk/
H A DKconfig54 This clock driver adds support for RCC clock management
94 bool "Enable RCC clock driver for STM32MP1"
98 Enable the STM32 clock (RCC) driver. Enable support for
/openbmc/qemu/docs/system/arm/
H A Dstm32.rst39 * Reset and Clock Controller (RCC) (STM32F4 only, reset and enable only)
57 * Reset and Clock Controller (RCC) (other features than reset and enable)
H A Db-l475e-iot01a.rst20 - STM32L4x5 RCC (Reset and clock control)
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dst,stm32mp1-rcc.txt4 The RCC IP is both a reset and a clock controller.
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
/openbmc/u-boot/doc/device-tree-bindings/reset/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
/openbmc/qemu/hw/misc/
H A Dtrace-events195 stm32l4x5_rcc_read(uint64_t addr, uint32_t data) "RCC: Read <0x%" PRIx64 "> -> 0x%" PRIx32
196 stm32l4x5_rcc_write(uint64_t addr, uint32_t data) "RCC: Write <0x%" PRIx64 "> <- 0x%" PRIx32
197 stm32l4x5_rcc_mux_enable(uint32_t mux_id) "RCC: Mux %d enabled"
198 stm32l4x5_rcc_mux_disable(uint32_t mux_id) "RCC: Mux %d disabled"
199 …ier, uint32_t new_multiplier, uint32_t old_divider, uint32_t new_divider) "RCC: Mux %d factor chan…
200 stm32l4x5_rcc_mux_set_src(uint32_t mux_id, uint32_t old_src, uint32_t new_src) "RCC: Mux %d source …
201 …, uint32_t src, uint64_t src_freq, uint32_t multiplier, uint32_t divider) "RCC: Mux %d src %d upda…
202 …iplier(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multip…
203 stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u ena…
204 stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u di…
[all …]
/openbmc/qemu/tests/qtest/
H A Dcmsdk-apb-watchdog-test.c34 #define RCC 0x60 macro
146 rcc = readl(SSYS_BASE + RCC); in test_clock_change()
149 writel(SSYS_BASE + RCC, rcc); in test_clock_change()
/openbmc/u-boot/drivers/misc/
H A DKconfig203 bool "Enable RCC driver for the STM32 SoC's family"
206 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
/openbmc/linux/drivers/reset/
H A DKconfig229 - RCC reset controller in STM32 MCUs
/openbmc/qemu/hw/net/
H A Dpcnet.c294 GET_FIELD((R)->msg_length, RMDM, RCC), \