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Searched refs:RCB_REG (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c229 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); in pch_power_options()
230 clrbits_le32(RCB_REG(0x3f02), 0xf); in pch_power_options()
258 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); in cpt_pm_init()
260 setbits_le32(RCB_REG(0x228c), 1 << 0); in cpt_pm_init()
261 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); in cpt_pm_init()
262 setbits_le32(RCB_REG(0x0900), 1 << 14); in cpt_pm_init()
263 writel(0xc0388400, RCB_REG(0x2304)); in cpt_pm_init()
264 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); in cpt_pm_init()
265 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); in cpt_pm_init()
266 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); in cpt_pm_init()
[all …]
H A Dsdram.c374 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); in rcba_config()
375 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); in rcba_config()
376 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); in rcba_config()
377 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); in rcba_config()
378 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); in rcba_config()
379 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); in rcba_config()
380 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); in rcba_config()
381 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); in rcba_config()
384 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); in rcba_config()
385 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR)); in rcba_config()
[all …]
H A Dbd82x6x.c104 data = readl(RCB_REG(IOBPS)); in iobp_poll()
120 writel(address, RCB_REG(IOBPIRI)); in pch_iobp_update()
124 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); in pch_iobp_update()
126 writel(IOBPS_READ_AX, RCB_REG(IOBPS)); in pch_iobp_update()
131 data = readl(RCB_REG(IOBPD)); in pch_iobp_update()
136 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { in pch_iobp_update()
147 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); in pch_iobp_update()
149 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); in pch_iobp_update()
154 writel(data, RCB_REG(IOBPD)); in pch_iobp_update()
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c51 writew(0x1000, RCB_REG(OIC)); in broadwell_pch_early_init()
53 readw(RCB_REG(OIC)); in broadwell_pch_early_init()
56 clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7); in broadwell_pch_early_init()
58 readl(RCB_REG(HPTC)); in broadwell_pch_early_init()
62 setbits_le32(RCB_REG(GCS), 1 << 5); in broadwell_pch_early_init()
100 setbits_le32(RCB_REG(0x3310), 0x0000002f); in pch_misc_init()
101 clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0); in pch_misc_init()
103 setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); in pch_misc_init()
104 setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); in pch_misc_init()
211 clrbits_le32(RCB_REG(0x232c), 1), in pch_pm_init_magic()
[all …]
H A Diobp.c35 u16 status = readw(RCB_REG(IOBPS)); in iobp_poll()
51 writel(address, RCB_REG(IOBPIRI)); in pch_iobp_trans_start()
54 clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op); in pch_iobp_trans_start()
64 writew(IOBPU_MAGIC, RCB_REG(IOBPU)); in pch_iobp_trans_finish()
67 setbits_le16(RCB_REG(IOBPS), IOBPS_READY); in pch_iobp_trans_finish()
73 status = readw(RCB_REG(IOBPS)); in pch_iobp_trans_finish()
90 return readl(RCB_REG(IOBPD)); in pch_iobp_read()
98 writel(data, RCB_REG(IOBPD)); in pch_iobp_write()
128 writel(addr, RCB_REG(IOBPIRI)); in pch_iobp_exec()
129 clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code); in pch_iobp_exec()
[all …]
H A Dsata.c110 reg32 = readl(RCB_REG(0x3a84)); in broadwell_sata_init()
117 writel(reg32, RCB_REG(0x3a84)); in broadwell_sata_init()
193 clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000); in broadwell_sata_init()
H A Dadsp.c88 setbits_le32(RCB_REG(0x3350), 1 << 10); in broadwell_adsp_probe()
101 setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN); in broadwell_adsp_probe()
H A Dcpu.c349 pmsync = readl(RCB_REG(PMSYNC_CONFIG)); in configure_pch_power_sharing()
350 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2)); in configure_pch_power_sharing()
364 writel(pmsync, RCB_REG(PMSYNC_CONFIG)); in configure_pch_power_sharing()
382 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2)); in configure_pch_power_sharing()
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dcpu.c50 writel(1 << 2, RCB_REG(RC)); in cpu_common_init()
97 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, in cpu_set_flex_ratio_to_tdp_nominal()
103 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1); in cpu_set_flex_ratio_to_tdp_nominal()
H A Dlpc.c33 clrbits_le32(RCB_REG(GCS), 4); in enable_port80_on_lpc()
/openbmc/u-boot/arch/x86/include/asm/
H A Dintel_regs.h22 #define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg)) macro
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dspi.h17 #define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
/openbmc/u-boot/drivers/video/
H A Divybridge_igd.c729 writew(0x0010, RCB_REG(DISPBDF)); in gma_func0_init()
730 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); in gma_func0_init()