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Searched refs:R5 (Results 1 – 25 of 58) sorted by relevance

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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a.dtsi84 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
85 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
86 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
87 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
93 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
94 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
101 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
102 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
114 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
115 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
H A Dk3-am62p.dtsi99 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
100 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
113 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
114 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
/openbmc/u-boot/board/ti/am65x/
H A DREADME20 On AM65x family devices, ROM supports boot only via MCU(R5). This means that
21 bootloader has to run on R5 core. In order to meet this constraint, and for
23 1. Need to move away from R5 asap, so that we want to start *any*
33 | DMSC | R5 | A53 |
46 | | | | | *R5 ROM* | | |
55 | | | | | *R5 SPL* | | |
101 - Here DMSC acts as master and provides all the critical services. R5/A53
135 4.1. R5:
159 | | R5 | |
H A DKconfig16 bool "TI K3 based AM654 EVM running on R5"
/openbmc/linux/drivers/tty/serial/
H A Dpmac_zilog.c135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
167 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
539 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
540 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
542 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
544 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
677 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
678 uap->curregs[R5] = new_reg; in pmz_break_ctl()
679 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
[all …]
H A Dip22zilog.c188 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
221 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
560 up->curregs[R5] |= set_bits; in ip22zilog_set_mctrl()
561 up->curregs[R5] &= ~clear_bits; in ip22zilog_set_mctrl()
562 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_set_mctrl()
669 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in ip22zilog_break_ctl()
670 if (new_reg != up->curregs[R5]) { in ip22zilog_break_ctl()
671 up->curregs[R5] = new_reg; in ip22zilog_break_ctl()
674 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_break_ctl()
724 up->curregs[R5] |= TxENAB; in __ip22zilog_startup()
[all …]
H A Dsunzilog.c207 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
254 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
660 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
661 up->curregs[R5] &= ~clear_bits; in sunzilog_set_mctrl()
662 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_set_mctrl()
769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
770 if (new_reg != up->curregs[R5]) { in sunzilog_break_ctl()
771 up->curregs[R5] = new_reg; in sunzilog_break_ctl()
774 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_break_ctl()
789 up->curregs[R5] |= TxENAB; in __sunzilog_startup()
[all …]
H A Dzs.c270 write_zsreg(zport, R5, regs[5] & ~TxENAB); in load_zsregs()
285 write_zsreg(zport, R5, regs[5]); in load_zsregs()
402 write_zsreg(zport_a, R5, zport_a->regs[5]); in zs_set_mctrl()
526 write_zsreg(zport, R5, zport->regs[5]); in zs_break_ctl()
791 write_zsreg(zport, R5, zport->regs[5]); in zs_startup()
815 write_zsreg(zport, R5, zport->regs[5]); in zs_shutdown()
972 write_zsreg(zport, R5, zport->regs[5]); in zs_pm()
1165 write_zsreg(zport, R5, zport->regs[5]); in zs_console_write()
1177 write_zsreg(zport, R5, zport->regs[5]); in zs_console_write()
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7r/
H A Dtune-cortexr5.inc2 # Tune Settings for Cortex-R5
6 TUNEVALID[cortexr5] = "Enable Cortex-R5 specific processor optimizations"
/openbmc/linux/tools/perf/arch/arm/tests/
H A Dregs_load.S9 #define R5 0x28 macro
46 str r5, [r0, #R5]
/openbmc/linux/Documentation/bpf/standardization/
H A Dabi.rst20 * R1 - R5: arguments for function calls
24 R0 - R5 are scratch registers and BPF programs needs to spill/fill them if
/openbmc/linux/tools/perf/arch/powerpc/tests/
H A Dregs_load.S10 #define R5 5 * 8 macro
49 std 5, R5(3)
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-r5.dts3 * dts file for Xilinx ZynqMP R5
16 model = "Xilinx ZynqMP R5";
/openbmc/linux/lib/
H A Dtest_bpf.c44 #define R5 BPF_REG_5 macro
1623 i += __bpf_ld_imm64(&insns[i], R5, keep); in __bpf_emit_atomic64()
1635 insns[i++] = BPF_JMP_REG(BPF_JEQ, R0, R5, 1); in __bpf_emit_atomic64()
1670 i += __bpf_ld_imm64(&insns[i], R5, keep); in __bpf_emit_atomic32()
1682 insns[i++] = BPF_JMP_REG(BPF_JEQ, R0, R5, 1); in __bpf_emit_atomic32()
3783 BPF_ALU64_IMM(BPF_MOV, R5, 5),
3793 BPF_ALU64_IMM(BPF_ADD, R5, 20),
3803 BPF_ALU64_IMM(BPF_SUB, R5, 10),
3813 BPF_ALU64_REG(BPF_ADD, R0, R5),
3825 BPF_ALU64_REG(BPF_ADD, R1, R5),
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_entry.S57 { memd(R0 + #_PT_R0504) = R5:4; \
100 memd(R0 + #_PT_R0504) = R5:4; \
136 { R5:4 = memd(R0 + #_PT_R0504); \
168 { R5:4 = memd(R0 + #_PT_R0504); \
/openbmc/linux/arch/powerpc/platforms/pseries/
H A DhvCall.S38 std r5,STK_PARAM(R5)(r1); \
50 ld r5,STACK_FRAME_MIN_SIZE+STK_PARAM(R5)(r1); \
185 HCALL_INST_PRECALL(R5)
294 HCALL_INST_PRECALL(R5)
/openbmc/linux/drivers/net/hamradio/
H A Dscc.c805 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */ in init_channel()
937 or(scc,R5, TxENAB); in scc_key_trx()
938 scc->wreg[R5] |= RTS; in scc_key_trx()
940 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ in scc_key_trx()
943 cl(scc,R5,RTS|TxENAB); in scc_key_trx()
971 or(scc,R5, TxENAB); in scc_key_trx()
972 scc->wreg[R5] |= RTS; in scc_key_trx()
974 or(scc,R5,RTS|TxENAB); /* enable tx */ in scc_key_trx()
977 cl(scc,R5,RTS|TxENAB); /* disable tx */ in scc_key_trx()
1110 if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) ) in is_grouped()
[all …]
/openbmc/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
65 place function arguments into R1 to R5 registers to satisfy calling
67 to in-kernel function. If R1 - R5 registers are mapped to CPU registers
74 After an in-kernel function call, R1 - R5 are reset to unreadable and R0 has
123 R5 - r8
139 bpf_mov R5, 5
146 bpf_mov R5, 9
188 interpreter. R0-R5 are scratch registers, so eBPF program needs to preserve
198 After the call the registers R1-R5 contain junk values and cannot be read.
/openbmc/linux/arch/s390/crypto/
H A Dcrc32le-vx.S66 .octa 0x163cd6124 # R5
75 .octa 0x0dd45aab8 # R5
/openbmc/linux/drivers/media/i2c/
H A Dwm8739.c36 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator
221 wm8739_write(sd, R5, 0x000); in wm8739_probe()
/openbmc/linux/tools/perf/arch/arm/util/
H A Dunwind-libdw.c25 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/openbmc/linux/arch/hexagon/lib/
H A Dmemcpy.S164 #define ptr_in_p_128 R5 /* pointer for prefetch of input data */
167 #define shift2 R5 /* in epilog to workshifter to extract bytes */
177 #define ptr_in_p_128kernel R5:4 /* packed fetch pointer & kernel cnt */
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/anthy/anthy/
H A D2ch_t.patch98 +���� #R5 aga
117 +���� #R5 age
967 +���� #R5 ��
1008 +���� #R5 ����
1072 +���� #R5 ����
1165 +����� #R5 �����
1872 +�� #R5 ��
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[all …]
/openbmc/linux/tools/perf/arch/loongarch/util/
H A Dunwind-libdw.c27 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/openbmc/linux/tools/perf/arch/s390/util/
H A Dunwind-libdw.c31 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()

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