| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 51 POR
52 - support critical POR setting changed via switch on board
168 CPLD POR setting registers
170 1. Set POR switch selection register (addr 0xFFB00011) to 0.
171 2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
176 After reset, the new POR setting will be implemented.
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| H A D | README.P1010RDB-PB | 36 POR: support critical POR setting changed via switch on board
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| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-snps-eusb2.c | 22 #define POR BIT(1) macro
271 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR); in qcom_snps_eusb2_hsphy_init()
331 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0); in qcom_snps_eusb2_hsphy_init()
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| H A D | phy-qcom-snps-femto-v2.c | 31 #define POR BIT(1) macro
421 POR, POR); in qcom_snps_hsphy_init()
459 POR, 0); in qcom_snps_hsphy_init()
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| /openbmc/u-boot/doc/device-tree-bindings/input/ |
| H A D | i8042.txt | 10 duplicate POR byte, which should be ignored.
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| /openbmc/phosphor-state-manager/ |
| H A D | bmc_state_manager.cpp | 311 this->lastRebootCause(RebootCause::POR); in discoverLastRebootCause()
344 this->lastRebootCause(RebootCause::POR); in discoverLastRebootCause()
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | tx79.decode | 66 POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
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| /openbmc/docs/designs/ |
| H A D | bmc-reboot-cause-update.md | 85 | POR | 0x00 | Do nothing |
94 In the original approach, **WDIOF_CARDRESET** was used to represent a **POR**
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| /openbmc/linux/arch/arm/boot/dts/nxp/mxs/ |
| H A D | imx23-olinuxino.dts | 110 startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
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| /openbmc/qemu/hw/pci-host/ |
| H A D | sabre.c | 52 #define POR (1U << 31) macro
351 s->reset_control = POR; in sabre_reset()
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| /openbmc/linux/drivers/soc/fsl/ |
| H A D | Kconfig | 16 enabling, power-onreset(POR) configuration monitoring, alternate
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qdl-udoo.dtsi | 68 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
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| /openbmc/qemu/include/hw/misc/ |
| H A D | xlnx-versal-crl.h | 210 FIELD(RST_FPD, POR, 0, 1)
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mn-tqma8mqnl.dtsi | 238 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
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| H A D | imx8mq-tqma8mq.dtsi | 276 /* Attention: wdog reset forcing POR needs baseboard support */
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| H A D | imx8mm-tqma8mqml.dtsi | 254 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
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| /openbmc/linux/Documentation/translations/sp_SP/process/ |
| H A D | kernel-docs.rst | 25 POR FAVOR, si conoce algún documento que no figura aquí, o si escribe un
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| H A D | coding-style.rst | 632 posiblemente POR QUÉ hace esto.
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| /openbmc/linux/Documentation/ABI/stable/ |
| H A D | sysfs-driver-firmware-zynqmp | 42 Register is reset only by a POR reset.
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-pinephone-pro.dts | 119 * POR circuit.
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| /openbmc/u-boot/board/ti/am335x/ |
| H A D | README | 83 Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | decode-new.c.inc | 1194 [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */
1415 [0xeb] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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| H A D | emit.c.inc | 868 BINARY_INT_GVEC(POR, tcg_gen_gvec_or, MO_64)
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | x86.csv | 1574 "POR mm1, mm2/m64","POR mm2/m64, mm1","por mm2/m64, mm1","0F EB /r","V","V","MMX","","rw,r","",""
1575 "POR xmm1, xmm2/m128","POR xmm2/m128, xmm1","por xmm2/m128, xmm1","66 0F EB /r","V","V","SSE2","","…
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