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Searched refs:PL1_W (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/arm/
H A Dhelper.c692 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
702 .access = PL1_W, .type = ARM_CP_WFI },
711 .access = PL1_W, .type = ARM_CP_WFI },
740 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
743 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
746 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
749 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
865 .access = PL1_W, .type = ARM_CP_NOP },
2088 .access = PL1_W, .type = ARM_CP_NOP },
2336 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
[all …]
H A Dcpregs.h286 PL1_W = 0x04 | PL2_W, enumerator
288 PL0_W = 0x01 | PL1_W,
304 PL1_RW = PL1_R | PL1_W,
H A Ddebug_helper.c1015 .access = PL1_W, .type = ARM_CP_NO_RAW,
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
582 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
701 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
704 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
707 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
710 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
713 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
716 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2463 .access = PL1_W, .accessfn = gicv3_fiq_access,
2497 .access = PL1_W, .accessfn = gicv3_dir_access,
2509 .access = PL1_W, .accessfn = gicv3_sgi_access,
2515 .access = PL1_W, .accessfn = gicv3_sgi_access,
2521 .access = PL1_W, .accessfn = gicv3_sgi_access,
2527 .access = PL1_W, .accessfn = gicv3_sgi_access,
2533 .access = PL1_W, .accessfn = gicv3_sgi_access,
2539 .access = PL1_W, .accessfn = gicv3_sgi_access,
2551 .access = PL1_W, .accessfn = gicv3_irq_access,