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Searched refs:PIPE_C (Results 1 – 25 of 27) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c123 MMIO_D(PIPEDSL(PIPE_C)); in iterate_generic_mmio()
131 MMIO_D(PIPESTAT(PIPE_C)); in iterate_generic_mmio()
135 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C)); in iterate_generic_mmio()
139 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C)); in iterate_generic_mmio()
143 MMIO_D(CURCNTR(PIPE_C)); in iterate_generic_mmio()
146 MMIO_D(CURPOS(PIPE_C)); in iterate_generic_mmio()
149 MMIO_D(CURBASE(PIPE_C)); in iterate_generic_mmio()
152 MMIO_D(CUR_FBC_CTL(PIPE_C)); in iterate_generic_mmio()
178 MMIO_D(DSPCNTR(PIPE_C)); in iterate_generic_mmio()
179 MMIO_D(DSPADDR(PIPE_C)); in iterate_generic_mmio()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c125 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
132 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
139 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
370 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
404 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
424 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
441 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
464 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
488 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
544 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all …]
H A Dskl_watermark.c863 .active_pipes = BIT(PIPE_C),
865 [PIPE_C] = BIT(DBUF_S2),
869 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
872 [PIPE_C] = BIT(DBUF_S2),
876 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
879 [PIPE_C] = BIT(DBUF_S2),
883 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
887 [PIPE_C] = BIT(DBUF_S2),
926 .active_pipes = BIT(PIPE_C),
928 [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
[all …]
H A Dintel_display_limits.h19 PIPE_C, enumerator
36 TRANSCODER_C = PIPE_C,
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
395 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
475 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
579 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
793 .irq_pipe_mask = BIT(PIPE_C),
945 .irq_pipe_mask = BIT(PIPE_C),
1089 .irq_pipe_mask = BIT(PIPE_C),
1185 .irq_pipe_mask = BIT(PIPE_C),
1360 .irq_pipe_mask = BIT(PIPE_C),
1518 .irq_pipe_mask = BIT(PIPE_C),
H A Dintel_display_trace.h49 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
78 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
185 __entry->frame[PIPE_C], __entry->scanline[PIPE_C])
H A Di9xx_wm.c284 case PIPE_C: in vlv_get_fifo_size()
786 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
787 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
789 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
790 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
793 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
794 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
795 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1650 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; in _vlv_compute_pipe_wm()
1821 case PIPE_C: in vlv_atomic_update_fifo()
[all …]
H A Dintel_fdi.c171 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_C); in ilk_check_fdi_lanes()
184 case PIPE_C: in ilk_check_fdi_lanes()
297 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
325 case PIPE_C: in ivb_update_fdi_bc_bifurcation()
H A Dintel_pipe_crc.c180 case PIPE_C: in vlv_pipe_crc_ctl_reg()
241 case PIPE_C: in vlv_undo_pipe_scramble_reset()
H A Dintel_display_power_well.c1425 pipe = PIPE_C; in chv_dpio_cmn_power_well_enable()
1491 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable()
1513 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
H A Dskl_universal_plane.c1968 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) in skl_plane_has_planar()
2181 return pipe != PIPE_C; in skl_plane_has_rc_ccs()
2183 return pipe != PIPE_C && in skl_plane_has_rc_ccs()
H A Dintel_display_irq.c446 case PIPE_C: in i9xx_pipestat_irq_ack()
942 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
H A Dg4x_hdmi.c756 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
H A Dintel_cursor.c475 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && in i9xx_check_cursor()
H A Dicl_dsi.c815 case PIPE_C: in gen11_dsi_configure_transcoder()
1704 *pipe = PIPE_C; in gen11_dsi_get_hw_state()
H A Dintel_dpio_phy.c676 case PIPE_C: in vlv_pipe_to_channel()
H A Dintel_dmc.c446 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) in adlp_pipedmc_clock_gating_wa()
H A Dg4x_dp.c1362 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
H A Dvlv_dsi.c988 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
H A Dintel_display.c2567 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_transcoder_timings()
3375 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); in bigjoiner_pipes()
3377 pipes = BIT(PIPE_B) | BIT(PIPE_C); in bigjoiner_pipes()
3528 trans_pipe = PIPE_C; in hsw_enabled_transcoders()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c892 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
895 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
898 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
1006 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
1029 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
2280 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2281 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2289 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2290 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2311 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); in init_generic_mmio_info()
[all …]
H A Dreg.h75 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
83 (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
H A Ddisplay.c56 pipe = PIPE_C; in get_edp_pipe()
629 [PIPE_C] = PIPE_C_VBLANK, in emulate_vblank_on_pipe()
633 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
H A Dinterrupt.c493 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
H A Dcmd_parser.c1293 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1294 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1352 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
1367 info->pipe = PIPE_C; in skl_decode_mi_display_flip()

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