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Searched refs:PHYS_SDRAM_1 (Results 1 – 25 of 138) sorted by relevance

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/openbmc/u-boot/include/configs/
H A Dlegoev3.h30 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
35 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
38 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
64 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
70 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dea20.h35 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
40 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
43 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
92 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
98 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dmx25pdk.h31 #define PHYS_SDRAM_1 0x80000000 macro
34 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
44 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
45 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
H A Dda850evm.h48 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
53 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
56 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
224 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
230 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Domapl138_lcdk.h42 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
47 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
50 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
213 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
219 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dbcm_northstar2.h15 #define PHYS_SDRAM_1 V2M_BASE macro
19 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
22 #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00)
H A Dedb93xx.h132 #define PHYS_SDRAM_1 0x00000000 macro
135 #define PHYS_SDRAM_1 0xc0000000 macro
138 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
144 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dcalimain.h107 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
119 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
160 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
167 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dstih410-b2260.h13 #define PHYS_SDRAM_1 0x40000000 macro
14 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
16 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */
H A Dipam390.h34 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ macro
39 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
173 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
179 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
H A Dvexpress_aemv8a.h122 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ macro
126 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
134 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
135 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
H A Dcolibri_pxa270.h87 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ macro
96 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
97 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dts4600.h19 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
21 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dbg0900.h9 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
11 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dsansa_fuze_plus.h11 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
13 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dmx23_olinuxino.h14 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
16 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
H A Dxfi3.h11 #define PHYS_SDRAM_1 0x40000000 /* Base address */ macro
13 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dmx53_dram.c24 return get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); in get_effective_memsize()
29 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); in dram_init()
37 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
38 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); in dram_init_banksize()
/openbmc/u-boot/arch/arm/mach-imx/imx8/
H A Dcpu.c226 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; in get_effective_memsize()
237 if (start >= PHYS_SDRAM_1 && start <= end1 && in get_effective_memsize()
240 if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 + in get_effective_memsize()
242 return (end - PHYS_SDRAM_1 + 1); in get_effective_memsize()
258 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; in dram_init()
268 if (start >= PHYS_SDRAM_1 && start <= end1) { in dram_init()
320 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE; in dram_init_banksize()
330 if (start >= PHYS_SDRAM_1 && start <= end1) { in dram_init_banksize()
358 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
372 if ((addr_start >= PHYS_SDRAM_1 && in get_block_attrs()
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/openbmc/u-boot/board/cirrus/edb93xx/
H A Dedb93xx.c128 dram_bank_base[0] = PHYS_SDRAM_1; in dram_fill_bank_addr()
151 unsigned addr = PHYS_SDRAM_1; in dram_fill_bank_addr()
176 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE); in dram_init_banksize_int()
178 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK); in dram_init_banksize_int()
180 (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT); in dram_init_banksize_int()
/openbmc/u-boot/board/samsung/smdkc100/
H A Dsmdkc100.c42 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; in board_init()
49 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); in dram_init()
56 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
/openbmc/u-boot/board/samsung/smdkv310/
H A Dsmdkv310.c40 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); in board_init()
46 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) in dram_init()
56 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
57 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, in dram_init_banksize()
/openbmc/u-boot/board/armadeus/apf27/
H A Dapf27.c171 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; in board_init()
187 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); in dram_init()
197 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
198 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, in dram_init_banksize()
218 ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1, in board_get_usable_ram_top()
H A Dlowlevel_init.S92 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
98 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
109 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
113 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
/openbmc/u-boot/board/compulab/cm_fx6/
H A Dspl.c236 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); in cm_fx6_spl_dram_init()
247 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); in cm_fx6_spl_dram_init()
257 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); in cm_fx6_spl_dram_init()
275 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); in cm_fx6_spl_dram_init()
280 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); in cm_fx6_spl_dram_init()

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