Searched refs:PCIe (Results 1 – 25 of 481) sorted by relevance
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3 menu "DesignWare-based PCIe controllers"18 bool "Amazon Annapurna Labs PCIe controller"24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare28 Annapurna Labs PCIe controller don't need to enable this.31 tristate "Amlogic Meson PCIe controller"45 bool "Axis ARTPEC-6 PCIe controller (host mode)"51 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in55 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"61 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in[all …]
3 menu "Cadence-based PCIe controllers"25 bool "Cadence platform PCIe controller (host mode)"30 Say Y here if you want to support the Cadence PCIe platform controller in31 host mode. This PCIe controller may be embedded into many different35 bool "Cadence platform PCIe controller (endpoint mode)"41 Say Y here if you want to support the Cadence PCIe platform controller in42 endpoint mode. This PCIe controller may be embedded into many49 bool "TI J721E PCIe controller (host mode)"54 Say Y here if you want to support the TI J721E PCIe platform55 controller in host mode. TI J721E PCIe controller uses Cadence PCIe[all …]
7 tristate "Aardvark PCIe controller"13 Add support for Aardvark 64bit PCIe Host Controller. This18 tristate "Altera PCIe controller"21 Say Y here if you want to enable PCIe controller support on Altera25 tristate "Altera PCIe MSI feature"29 Say Y here if you want PCIe MSI support for the Altera FPGA.38 tristate "Apple PCIe controller"44 Say Y here if you want to enable PCIe controller support on Apple55 tristate "Broadcom Brcmstb PCIe controller"62 Say Y here to enable PCIe host controller support for[all …]
25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.35 0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space.39 0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space.41 0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space.43 0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space.45 0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space.[all …]
14 1 pex0_en PCIe 0 Clock out15 2 pex1_en PCIe 1 Clock out18 5 pex0 PCIe Cntrl 019 9 pex1 PCIe Cntrl 133 5 pex0 PCIe 0 Clock out34 6 pex1 PCIe 1 Clock out61 5 pex1 PCIe 162 6 pex2 PCIe 263 7 pex3 PCIe 364 8 pex0 PCIe 0[all …]
30 bool "Enable Aardvark PCIe driver"35 Say Y here if you want to enable PCIe controller support on36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on47 bool "Enable Aspeed PCIe driver"51 Say Y here if you want to enable PCIe controller support on60 PCIe host controllers, such as the one emulated by QEMU.63 bool "Enable Armada-8K PCIe driver (DesignWare core)"67 Say Y here if you want to enable PCIe controller support on68 Armada-8K SoCs. The PCIe controller on Armada-8K is based on72 bool "Renesas RCar Gen2 PCIe driver"[all …]
19 This guide describes the basics of the PCI Express (PCIe) Advanced Error22 the PCIe AER driver.25 What is the PCIe AER Driver?28 PCIe error signaling can occur on the PCIe link itself29 or on behalf of transactions initiated on the link. PCIe32 required of all PCIe components providing a minimum defined34 capability is implemented with a PCIe Advanced Error Reporting37 The PCIe AER driver provides the infrastructure to support PCIe Advanced38 Error Reporting capability. The PCIe AER driver provides three basic45 The AER driver only attaches to Root Ports and RCECs that support the PCIe[all …]
1 Aardvark PCIe controller3 This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.5 The Device Tree node describing an Aardvark PCIe controller must9 - reg: range of registers for the PCIe controller10 - interrupts: the interrupt line of the PCIe controller16 - msi-controller: indicates that the PCIe controller can itself20 define the mapping of the PCIe interface to interrupt numbers.22 - phys: the PCIe PHY handle26 In addition, the Device Tree describing an Aardvark PCIe controller28 built into the PCIe controller. This sub-node must have the following
1 HiSilicon STB PCIe host bridge DT description3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.4 It shares common functions with the DesignWare PCIe core driver and inherits15 "control": control registers of PCIe controller;16 "rc-dbi": configuration space of PCIe controller;17 "config": configuration transaction space of PCIe controller.36 - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.37 - vpcie-supply: The regulator in charge of PCIe port power.
1 * Marvell Armada 7K/8K PCIe interface3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP14 - interrupts: Interrupt specifier for the PCIe controller15 - clocks: reference to the PCIe controller clocks23 PCIe lanes.
1 NVIDIA Tegra PCIe controller11 contain BPMP phandle and PCIe power partition ID. This is required only71 - "default": active state, puts PCIe I/O out of deep power down state72 - "idle": puts PCIe I/O into deep power down state85 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.86 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.87 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must91 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.95 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must99 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must[all …]
1 # Redfish PCIe Resources11 Redfish has resources that describe PCIe devices and functions available on a17 The Redfish PCIe resources are here:27 This feature is intended to meet the Redfish requirements for the PCIe resources34 model used in OpenBMC. The producer will provide the required PCIe values read36 the Redfish PCIe resources.42 gathering and caching PCIe hardware data and maintaining the D-Bus interfaces43 and properties. The actual hardware mechanism that is used to gather the PCIe49 the required data and send it to the PCIe daemon through IPMI, etc.51 When reading hardware directly, the PCIe daemon must be aware of power state[all …]
3 menu "Mobiveil-based PCIe controllers"15 bool "Freescale Layerscape Gen4 PCIe controller"20 Say Y here if you want PCIe Gen4 controller support on24 bool "Mobiveil AXI PCIe controller"30 Say Y here if you want to enable support for the Mobiveil AXI PCIe32 for address translation and it is a PCIe Gen4 IP.
7 The solution is working well on several OEM products. AMD SFH uses HID over PCIe bus.35 | AMD MP2 PCIe Driver |58 interface between MP2 PCIe layer and HID. HID client layer initializes the MP2 PCIe layer and holds59 the instance of MP2 layer. It identifies the number of sensors connected using MP2-PCIe layer. Based60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On65 AMD MP2 PCIe layer67 MP2 PCIe Layer is responsible for making all transactions with the firmware over PCIe.68 The connection establishment between firmware and PCIe happens here.85 HID AMD AMD AMD -PCIe MP290 | | | MP2-PCIe Int |
21 This is the driver for Realtek RTL8192CE/RTL8188CE 802.11n PCIe27 tristate "Realtek RTL8192SE/RTL8191SE PCIe Wireless Network Adapter"32 This is the driver for Realtek RTL8192SE/RTL8191SE 802.11n PCIe38 tristate "Realtek RTL8192DE/RTL8188DE PCIe Wireless Network Adapter"43 This is the driver for Realtek RTL8192DE/RTL8188DE 802.11n PCIe49 tristate "Realtek RTL8723AE PCIe Wireless Network Adapter"56 This is the driver for Realtek RTL8723AE 802.11n PCIe62 tristate "Realtek RTL8723BE PCIe Wireless Network Adapter"69 This is the driver for Realtek RTL8723BE 802.11n PCIe80 This is the driver for Realtek RTL8188EE 802.11n PCIe[all …]
2 HiSilicon PCIe Performance Monitoring Unit (PMU)5 On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.8 Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and12 HiSilicon PCIe PMU driver15 The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe45 Also attach to a task is unsupported for PCIe PMU.53 Ports or downstream target Endpoint. PCIe PMU driver support "port" and59 "port" filter can be used in all PCIe PMU events, target Root Port can be
3 tristate "HiSilicon PCIe Tune and Trace Device"7 HiSilicon PCIe Tune and Trace device exists as a PCIe RCiEP8 device, and it provides support for PCIe traffic tuning and
5 Description: Allows the user to enable the PCIe traffic generator which7 Endpoint direction or to disable the PCIe traffic generator17 The user can read the current PCIe link throughput generated30 Description: Allows the user to enable the PCIe traffic generator which32 Complex direction or to disable the PCIe traffic generator42 The user can read the current PCIe link throughput generated
29 bool "Apalis Evaluation Board PCIe Initialisation"31 Bring up the Apalis PCIe port with the PCIe switch as found on the32 Apalis Evaluation board. Note that by default the PCIe port is also
4 Spear PCIe Gadget Driver24 PCIe gadget support for SPEAr13XX platform29 Its main purpose is to configure selected dual mode PCIe controller as device31 type. This driver can be used to show spear's PCIe device capability.78 Program all PCIe registers in such a way that when this device is connected79 to the PCIe host, then host sees this device as 1MB RAM.85 For nth PCIe Device Controller::107 memory, which is to be made visible to PCIe host. Similarly any other peripheral108 can also be made visible to PCIe host. E.g., if you program base address of UART125 is initialized and start to search PCIe devices on its port.
19 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential23 * the USB3.0 controller and the PCIe Controller, thus only25 * If the MCU is configured to mux the PCIe/USB3.0 differential lines27 * USB3.0 from the USB Complex and enable the PCIe controller.30 * update these nodes accordingly if PCIe mode is selected by the MCU.
29 bool "Apalis Evaluation Board PCIe Initialisation"31 Bring up the Apalis type specific 4 lane PCIe port as well as the32 Apalis PCIe port with the PCIe switch as found on the Apalis
4 HiSilicon PCIe Tune and Trace device10 HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex12 to dynamically monitor and tune the PCIe link's events (tune),15 PCIe link's performance.17 On Kunpeng 930 SoC, the PCIe Root Complex is composed of several18 PCIe cores. Each PCIe core includes several Root Ports and a PTT20 tracing the links of the PCIe core.39 IO dies (SICL, Super I/O Cluster), where there's one PCIe Root48 PTT tune is designed for monitoring and adjusting PCIe link parameters (events).50 covers the PCIe core to which the PTT device belongs.[all …]
16 PCIe, enumerator33 PCIe, enumerator64 {CableClass::PCIe, "PCIe"},81 {ConnectorType::PCIe, "PCIe"},