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Searched refs:PCIE500_REG_BASE (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/pci-host/
H A Dppce500.c36 #define PCIE500_REG_BASE 0xC00 macro
38 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
46 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
47 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
48 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
49 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
50 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
51 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
52 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
54 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
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