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Searched refs:PBS_RX_MODE (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c42 (pbs_mode == PBS_RX_MODE) ? HWS_HIGH2LOW : HWS_LOW2HIGH; in ddr3_tip_pbs()
43 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE; in ddr3_tip_pbs()
44 int iterations = (pbs_mode == PBS_RX_MODE) ? 31 : 63; in ddr3_tip_pbs()
45 u32 res_valid_mask = (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f; in ddr3_tip_pbs()
72 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
85 validation_val = (pbs_mode == PBS_RX_MODE) ? 0x1f : 0; in ddr3_tip_pbs()
91 (pbs_mode == PBS_RX_MODE) ? 0x1f : 0x3f; in ddr3_tip_pbs()
144 (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
166 (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
186 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
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H A Dddr3_training_ip_pbs.h32 PBS_RX_MODE, enumerator
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_hw_training.c709 mode_config[PBS_RX_MODE] = PUP_PBS_RX; in ddr3_save_training()
732 i == PBS_RX_MODE) { in ddr3_save_training()
H A Dddr3_hw_training.h282 PBS_RX_MODE, enumerator