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Searched refs:NUM_CHANNELS (Results 1 – 18 of 18) sorted by relevance

/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
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/openbmc/u-boot/drivers/pwm/
H A Dsandbox_pwm.c14 NUM_CHANNELS = 3, enumerator
33 struct sandbox_pwm_chan chan[NUM_CHANNELS];
42 if (channel >= NUM_CHANNELS) in sandbox_pwm_get_config()
59 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_config()
74 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_enable()
88 if (channel >= NUM_CHANNELS) in sandbox_pwm_set_invert()
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_rf.h26 #define NUM_CHANNELS 15 macro
30 u8 channel_set[NUM_CHANNELS];
31 u8 channel_cck_power[NUM_CHANNELS]; /*dbm*/
32 u8 channel_ofdm_power[NUM_CHANNELS];/*dbm*/
/openbmc/linux/drivers/staging/most/i2c/
H A Di2c.c18 enum { CH_RX, CH_TX, NUM_CHANNELS }; enumerator
36 struct most_channel_capability capabilities[NUM_CHANNELS];
74 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in configure_channel()
128 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in enqueue()
173 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in poison_channel()
303 for (i = 0; i < NUM_CHANNELS; i++) { in i2c_probe()
315 dev->most_iface.num_channels = NUM_CHANNELS; in i2c_probe()
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
303 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
934 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
970 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1006 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1058 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1356 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1384 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1411 uint32_t final_delay[NUM_CHANNELS][NUM_BYTE_LANES]; in rcvn_cal()
1445 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
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H A Dmrc_util.c1358 for (channel = 0; channel < NUM_CHANNELS; channel++) { in clear_pointers()
1455 for (channel = 0; channel < NUM_CHANNELS; channel++) { in print_timings()
/openbmc/linux/drivers/tty/serial/
H A Dip22zilog.c54 #define NUM_CHANNELS (NUM_IP22ZILOG * 2) macro
961 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); in ip22zilog_alloc_tables()
1069 .nr = NUM_CHANNELS,
1085 for (channel = 0; channel < NUM_CHANNELS; channel++) in ip22zilog_prepare()
1088 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; in ip22zilog_prepare()
1090 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) in ip22zilog_prepare()
1132 for (channel = 0; channel < NUM_CHANNELS; channel++) { in ip22zilog_prepare()
1169 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_ports_init()
1193 for (i = 0; i < NUM_CHANNELS; i++) { in ip22zilog_exit()
/openbmc/linux/drivers/edac/
H A Dskx_common.h50 #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS) macro
121 } chan[NUM_CHANNELS];
H A Digen6_edac.c45 #define NUM_CHANNELS 2 /* Max channels */ macro
151 u64 dimm_s_size[NUM_CHANNELS];
152 u64 dimm_l_size[NUM_CHANNELS];
153 int dimm_l_map[NUM_CHANNELS];
812 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_get_dimm_config()
879 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_reg_dump()
1021 layers[0].size = NUM_CHANNELS; in igen6_register_mci()
H A Dsb_edac.c286 #define NUM_CHANNELS 6 /* Max channels per MC */ macro
389 struct pci_dev *pci_tad[NUM_CHANNELS];
394 struct sbridge_channel channel[NUM_CHANNELS];
1592 : NUM_CHANNELS; in __populate_dimms()
1868 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()
1888 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout()
2379 if (channel >= NUM_CHANNELS) { in get_memory_error_data_from_mce()
3202 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); in sbridge_mce_output_error()
3358 KNL_MAX_CHANNELS : NUM_CHANNELS; in sbridge_register_mci()
H A Dskx_common.c491 layers[0].size = NUM_CHANNELS; in skx_register_mci()
744 for (j = 0; j < NUM_CHANNELS; j++) { in skx_remove()
/openbmc/linux/drivers/net/wireless/intersil/orinoco/
H A Dcfg.c59 for (i = 0; i < NUM_CHANNELS; i++) { in orinoco_wiphy_register()
183 if ((channel < 1) || (channel > NUM_CHANNELS) || in orinoco_set_monitor_channel()
H A Dhw.h21 #define NUM_CHANNELS 14 macro
H A Dhw.c1195 if ((channel < 1) || (channel > NUM_CHANNELS)) { in orinoco_hw_get_freq()
H A Dwext.c457 if ((chan < 1) || (chan > NUM_CHANNELS) || in orinoco_ioctl_setfreq()
/openbmc/u-boot/drivers/adc/
H A Dmeson-saradc.c161 #define NUM_CHANNELS 8 macro
623 if (channel < 0 || channel >= NUM_CHANNELS) { in meson_saradc_start_channel()
686 uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0); in meson_saradc_ofdata_to_platdata()
/openbmc/linux/drivers/clk/berlin/
H A Dberlin2-avpll.c29 #define NUM_CHANNELS 8 macro
/openbmc/linux/drivers/net/ethernet/toshiba/
H A Dps3_gelic_wireless.c52 #define NUM_CHANNELS ARRAY_SIZE(channel_freq) macro
315 i < NUM_CHANNELS && chs < IW_MAX_FREQUENCIES; i++) in gelic_wl_get_range()