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Searched refs:MTRR_VAR_PHYBASE (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/x86/cpu/quark/
H A Dquark.c48 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), in quark_setup_mtrr()
56 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM), in quark_setup_mtrr()
H A Ddram.c146 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), in dram_init()
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dquark.h69 #define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n)) macro