xref: /openbmc/u-boot/arch/x86/include/asm/arch-quark/quark.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2b994efbdSBin Meng /*
3b994efbdSBin Meng  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4b994efbdSBin Meng  */
5b994efbdSBin Meng 
6b994efbdSBin Meng #ifndef _QUARK_H_
7b994efbdSBin Meng #define _QUARK_H_
8b994efbdSBin Meng 
9b994efbdSBin Meng /* Message Bus Ports */
10b994efbdSBin Meng #define MSG_PORT_MEM_ARBITER	0x00
11b994efbdSBin Meng #define MSG_PORT_HOST_BRIDGE	0x03
12b994efbdSBin Meng #define MSG_PORT_RMU		0x04
13b994efbdSBin Meng #define MSG_PORT_MEM_MGR	0x05
14b06862b9SBin Meng #define MSG_PORT_USB_AFE	0x14
15316fd392SBin Meng #define MSG_PORT_PCIE_AFE	0x16
16b994efbdSBin Meng #define MSG_PORT_SOC_UNIT	0x31
17b994efbdSBin Meng 
18b162257dSBin Meng /* Port 0x00: Memory Arbiter Message Port Registers */
19b162257dSBin Meng 
20b162257dSBin Meng /* Enhanced Configuration Space */
21b162257dSBin Meng #define AEC_CTRL		0x00
22b162257dSBin Meng 
23b162257dSBin Meng /* Port 0x03: Host Bridge Message Port Registers */
24b162257dSBin Meng 
25f82a7840SBin Meng /* Host Miscellaneous Controls 2 */
26f82a7840SBin Meng #define HMISC2			0x03
27f82a7840SBin Meng 
28f82a7840SBin Meng #define HMISC2_SEGE		0x00000002
29f82a7840SBin Meng #define HMISC2_SEGF		0x00000004
30f82a7840SBin Meng #define HMISC2_SEGAB		0x00000010
31f82a7840SBin Meng 
32b994efbdSBin Meng /* Host Memory I/O Boundary */
33b994efbdSBin Meng #define HM_BOUND		0x08
34693b5f6cSBin Meng #define HM_BOUND_LOCK		0x00000001
35b994efbdSBin Meng 
36b162257dSBin Meng /* Extended Configuration Space */
37b162257dSBin Meng #define HEC_REG			0x09
38b162257dSBin Meng 
39c6d4705fSBin Meng /* MTRR Registers */
40c6d4705fSBin Meng #define MTRR_CAP		0x40
41c6d4705fSBin Meng #define MTRR_DEF_TYPE		0x41
42c6d4705fSBin Meng 
43c6d4705fSBin Meng #define MTRR_FIX_64K_00000	0x42
44c6d4705fSBin Meng #define MTRR_FIX_64K_40000	0x43
45c6d4705fSBin Meng #define MTRR_FIX_16K_80000	0x44
46c6d4705fSBin Meng #define MTRR_FIX_16K_90000	0x45
47c6d4705fSBin Meng #define MTRR_FIX_16K_A0000	0x46
48c6d4705fSBin Meng #define MTRR_FIX_16K_B0000	0x47
49c6d4705fSBin Meng #define MTRR_FIX_4K_C0000	0x48
50c6d4705fSBin Meng #define MTRR_FIX_4K_C4000	0x49
51c6d4705fSBin Meng #define MTRR_FIX_4K_C8000	0x4a
52c6d4705fSBin Meng #define MTRR_FIX_4K_CC000	0x4b
53c6d4705fSBin Meng #define MTRR_FIX_4K_D0000	0x4c
54c6d4705fSBin Meng #define MTRR_FIX_4K_D4000	0x4d
55c6d4705fSBin Meng #define MTRR_FIX_4K_D8000	0x4e
56c6d4705fSBin Meng #define MTRR_FIX_4K_DC000	0x4f
57c6d4705fSBin Meng #define MTRR_FIX_4K_E0000	0x50
58c6d4705fSBin Meng #define MTRR_FIX_4K_E4000	0x51
59c6d4705fSBin Meng #define MTRR_FIX_4K_E8000	0x52
60c6d4705fSBin Meng #define MTRR_FIX_4K_EC000	0x53
61c6d4705fSBin Meng #define MTRR_FIX_4K_F0000	0x54
62c6d4705fSBin Meng #define MTRR_FIX_4K_F4000	0x55
63c6d4705fSBin Meng #define MTRR_FIX_4K_F8000	0x56
64c6d4705fSBin Meng #define MTRR_FIX_4K_FC000	0x57
65c6d4705fSBin Meng 
66c6d4705fSBin Meng #define MTRR_SMRR_PHYBASE	0x58
67c6d4705fSBin Meng #define MTRR_SMRR_PHYMASK	0x59
68c6d4705fSBin Meng 
69c6d4705fSBin Meng #define MTRR_VAR_PHYBASE(n)	(0x5a + 2 * (n))
70c6d4705fSBin Meng #define MTRR_VAR_PHYMASK(n)	(0x5b + 2 * (n))
71c6d4705fSBin Meng 
72c6d4705fSBin Meng #ifndef __ASSEMBLY__
73c6d4705fSBin Meng 
74c6d4705fSBin Meng /* variable range MTRR usage */
75c6d4705fSBin Meng enum {
76c6d4705fSBin Meng 	MTRR_VAR_ROM,
77c6d4705fSBin Meng 	MTRR_VAR_ESRAM,
78c6d4705fSBin Meng 	MTRR_VAR_RAM
79c6d4705fSBin Meng };
80c6d4705fSBin Meng 
81c6d4705fSBin Meng #endif /* __ASSEMBLY__ */
82c6d4705fSBin Meng 
83b162257dSBin Meng /* Port 0x04: Remote Management Unit Message Port Registers */
84b162257dSBin Meng 
85b162257dSBin Meng /* ACPI PBLK Base Address Register */
86b162257dSBin Meng #define PBLK_BA			0x70
87b162257dSBin Meng 
88554778c2SBin Meng /* Control Register */
89554778c2SBin Meng #define RMU_CTRL		0x71
90554778c2SBin Meng 
91b162257dSBin Meng /* SPI DMA Base Address Register */
92b162257dSBin Meng #define SPI_DMA_BA		0x7a
93b162257dSBin Meng 
94554778c2SBin Meng /* Thermal Sensor Register */
95554778c2SBin Meng #define TS_MODE			0xb0
96554778c2SBin Meng #define TS_TEMP			0xb1
97554778c2SBin Meng #define TS_TRIP			0xb2
98554778c2SBin Meng 
99b162257dSBin Meng /* Port 0x05: Memory Manager Message Port Registers */
100b162257dSBin Meng 
101b994efbdSBin Meng /* eSRAM Block Page Control */
102b994efbdSBin Meng #define ESRAM_BLK_CTRL		0x82
103b994efbdSBin Meng #define ESRAM_BLOCK_MODE	0x10000000
104b994efbdSBin Meng 
105b06862b9SBin Meng /* Port 0x14: USB2 AFE Unit Port Registers */
106b06862b9SBin Meng 
107b06862b9SBin Meng #define USB2_GLOBAL_PORT	0x4001
108b06862b9SBin Meng #define USB2_PLL1		0x7f02
109b06862b9SBin Meng #define USB2_PLL2		0x7f03
110b06862b9SBin Meng #define USB2_COMPBG		0x7f04
111b06862b9SBin Meng 
112316fd392SBin Meng /* Port 0x16: PCIe AFE Unit Port Registers */
113316fd392SBin Meng 
114316fd392SBin Meng #define PCIE_RXPICTRL0_L0	0x2080
115316fd392SBin Meng #define PCIE_RXPICTRL0_L1	0x2180
116316fd392SBin Meng 
117316fd392SBin Meng /* Port 0x31: SoC Unit Port Registers */
118316fd392SBin Meng 
119554778c2SBin Meng /* Thermal Sensor Config */
120554778c2SBin Meng #define TS_CFG1			0x31
121554778c2SBin Meng #define TS_CFG2			0x32
122554778c2SBin Meng #define TS_CFG3			0x33
123554778c2SBin Meng #define TS_CFG4			0x34
124554778c2SBin Meng 
125316fd392SBin Meng /* PCIe Controller Config */
126316fd392SBin Meng #define PCIE_CFG		0x36
127316fd392SBin Meng #define PCIE_CTLR_PRI_RST	0x00010000
128316fd392SBin Meng #define PCIE_PHY_SB_RST		0x00020000
129316fd392SBin Meng #define PCIE_CTLR_SB_RST	0x00040000
130316fd392SBin Meng #define PCIE_PHY_LANE_RST	0x00090000
131316fd392SBin Meng #define PCIE_CTLR_MAIN_RST	0x00100000
132316fd392SBin Meng 
133b994efbdSBin Meng /* DRAM */
134b994efbdSBin Meng #define DRAM_BASE		0x00000000
135b994efbdSBin Meng #define DRAM_MAX_SIZE		0x80000000
136b994efbdSBin Meng 
137b994efbdSBin Meng /* eSRAM */
138b994efbdSBin Meng #define ESRAM_SIZE		0x80000
139b994efbdSBin Meng 
140b994efbdSBin Meng /* Memory BAR Enable */
141b994efbdSBin Meng #define MEM_BAR_EN		0x00000001
142b994efbdSBin Meng 
143b994efbdSBin Meng /* I/O BAR Enable */
144b994efbdSBin Meng #define IO_BAR_EN		0x80000000
145b994efbdSBin Meng 
146b994efbdSBin Meng /* 64KiB of RMU binary in flash */
147b994efbdSBin Meng #define RMU_BINARY_SIZE		0x10000
148b994efbdSBin Meng 
1492afb6230SBin Meng /* PCIe Root Port Configuration Registers */
1502afb6230SBin Meng 
1512afb6230SBin Meng #define PCIE_RP_CCFG		0xd0
1522afb6230SBin Meng #define CCFG_UPRS		(1 << 14)
1532afb6230SBin Meng #define CCFG_UNRS		(1 << 15)
1542afb6230SBin Meng #define CCFG_UNSD		(1 << 23)
1552afb6230SBin Meng #define CCFG_UPSD		(1 << 24)
1562afb6230SBin Meng 
1572afb6230SBin Meng #define PCIE_RP_MPC2		0xd4
1582afb6230SBin Meng #define MPC2_IPF		(1 << 11)
1592afb6230SBin Meng 
1602afb6230SBin Meng #define PCIE_RP_MBC		0xf4
1612afb6230SBin Meng #define MBC_SBIC		(3 << 16)
1622afb6230SBin Meng 
163b162257dSBin Meng /* Legacy Bridge PCI Configuration Registers */
164b162257dSBin Meng #define LB_GBA			0x44
165b162257dSBin Meng #define LB_PM1BLK		0x48
166b162257dSBin Meng #define LB_GPE0BLK		0x4c
167b162257dSBin Meng #define LB_ACTL			0x58
168b162257dSBin Meng #define LB_PABCDRC		0x60
169b162257dSBin Meng #define LB_PEFGHRC		0x64
170b162257dSBin Meng #define LB_WDTBA		0x84
171b162257dSBin Meng #define LB_BCE			0xd4
172b162257dSBin Meng #define LB_BC			0xd8
173b162257dSBin Meng #define LB_RCBA			0xf0
174b162257dSBin Meng 
1752afb6230SBin Meng /* USB EHCI memory-mapped registers */
1762afb6230SBin Meng #define EHCI_INSNREG01		0x94
1772afb6230SBin Meng 
1782afb6230SBin Meng /* USB device memory-mapped registers */
1792afb6230SBin Meng #define USBD_INT_MASK		0x410
1802afb6230SBin Meng #define USBD_EP_INT_STS		0x414
1812afb6230SBin Meng #define USBD_EP_INT_MASK	0x418
1822afb6230SBin Meng 
18305b98ec3SBin Meng #ifndef __ASSEMBLY__
18405b98ec3SBin Meng 
18505b98ec3SBin Meng /* Root Complex Register Block */
18605b98ec3SBin Meng struct quark_rcba {
18705b98ec3SBin Meng 	u32	rctl;
18805b98ec3SBin Meng 	u32	esd;
18905b98ec3SBin Meng 	u32	rsvd1[3150];
19005b98ec3SBin Meng 	u16	rmu_ir;
19105b98ec3SBin Meng 	u16	d23_ir;
19205b98ec3SBin Meng 	u16	core_ir;
19305b98ec3SBin Meng 	u16	d20d21_ir;
19405b98ec3SBin Meng };
19505b98ec3SBin Meng 
1965750e5e2SBin Meng #include <asm/io.h>
1975750e5e2SBin Meng #include <asm/pci.h>
1985750e5e2SBin Meng 
1995750e5e2SBin Meng /**
2005750e5e2SBin Meng  * qrk_pci_read_config_dword() - Read a configuration value
2015750e5e2SBin Meng  *
2025750e5e2SBin Meng  * @dev:	PCI device address: bus, device and function
2035750e5e2SBin Meng  * @offset:	Dword offset within the device's configuration space
2045750e5e2SBin Meng  * @valuep:	Place to put the returned value
2055750e5e2SBin Meng  *
2065750e5e2SBin Meng  * Note: This routine is inlined to provide better performance on Quark
2075750e5e2SBin Meng  */
qrk_pci_read_config_dword(pci_dev_t dev,int offset,u32 * valuep)2085750e5e2SBin Meng static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
2095750e5e2SBin Meng 					     u32 *valuep)
2105750e5e2SBin Meng {
2115750e5e2SBin Meng 	outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
2125750e5e2SBin Meng 	*valuep = inl(PCI_REG_DATA);
2135750e5e2SBin Meng }
2145750e5e2SBin Meng 
2155750e5e2SBin Meng /**
2165750e5e2SBin Meng  * qrk_pci_write_config_dword() - Write a PCI configuration value
2175750e5e2SBin Meng  *
2185750e5e2SBin Meng  * @dev:	PCI device address: bus, device and function
2195750e5e2SBin Meng  * @offset:	Dword offset within the device's configuration space
2205750e5e2SBin Meng  * @value:	Value to write
2215750e5e2SBin Meng  *
2225750e5e2SBin Meng  * Note: This routine is inlined to provide better performance on Quark
2235750e5e2SBin Meng  */
qrk_pci_write_config_dword(pci_dev_t dev,int offset,u32 value)2245750e5e2SBin Meng static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
2255750e5e2SBin Meng 					      u32 value)
2265750e5e2SBin Meng {
2275750e5e2SBin Meng 	outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
2285750e5e2SBin Meng 	outl(value, PCI_REG_DATA);
2295750e5e2SBin Meng }
2305750e5e2SBin Meng 
231316fd392SBin Meng /**
232316fd392SBin Meng  * board_assert_perst() - Assert the PERST# pin
233316fd392SBin Meng  *
234316fd392SBin Meng  * The CPU interface to the PERST# signal on Quark is platform dependent.
235316fd392SBin Meng  * Board-specific codes need supply this routine to assert PCIe slot reset.
236316fd392SBin Meng  *
237316fd392SBin Meng  * The tricky part in this routine is that any APIs that may trigger PCI
238316fd392SBin Meng  * enumeration process are strictly forbidden, as any access to PCIe root
239316fd392SBin Meng  * port's configuration registers will cause system hang while it is held
240316fd392SBin Meng  * in reset.
241316fd392SBin Meng  */
242316fd392SBin Meng void board_assert_perst(void);
243316fd392SBin Meng 
244316fd392SBin Meng /**
245316fd392SBin Meng  * board_deassert_perst() - De-assert the PERST# pin
246316fd392SBin Meng  *
247316fd392SBin Meng  * The CPU interface to the PERST# signal on Quark is platform dependent.
248316fd392SBin Meng  * Board-specific codes need supply this routine to de-assert PCIe slot reset.
249316fd392SBin Meng  *
250316fd392SBin Meng  * The tricky part in this routine is that any APIs that may trigger PCI
251316fd392SBin Meng  * enumeration process are strictly forbidden, as any access to PCIe root
252316fd392SBin Meng  * port's configuration registers will cause system hang while it is held
253316fd392SBin Meng  * in reset.
254316fd392SBin Meng  */
255316fd392SBin Meng void board_deassert_perst(void);
256316fd392SBin Meng 
25705b98ec3SBin Meng #endif /* __ASSEMBLY__ */
25805b98ec3SBin Meng 
259b994efbdSBin Meng #endif /* _QUARK_H_ */
260