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Searched refs:MT (Results 1 – 25 of 67) sorted by relevance

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/openbmc/linux/arch/sh/lib/
H A Dmemcpy-sh4.S31 mov r4,r2 ! 5 MT (0 cycles latency)
41 mov r7, r3 ! 5 MT (latency=0) ! RQPO
43 cmp/hi r2,r0 ! 57 MT
46 mov r1,r6 ! 5 MT (latency=0)
50 mov r1, r7 ! 5 MT (latency=0)
58 mov r7,r3 ! 5 MT (latency=0) ! OPQR
60 cmp/hi r2,r0 ! 57 MT
64 mov r1,r6 ! 5 MT (latency=0)
67 mov r1,r7 ! 5 MT (latency=0)
77 cmp/eq r4,r0 ! 54 MT
[all …]
H A Dmemset-sh4.S38 mov #0x40, r0 ! (MT)
39 cmp/gt r6,r0 ! (MT) 64 > len => slow loop
/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dworkqueue.rst40 在最初的wq实现中，多线程（MT）wq在每个CPU上有一个工作者线程，而单线程
41 （ST）wq在全系统有一个工作者线程。一个MT wq需要保持与CPU数量相同的工
42 作者数量。这些年来，内核增加了很多MT wq的用户，随着CPU核心数量的不断
45 尽管MT wq浪费了大量的资源，但所提供的并发性水平却不能令人满意。这个限
46 制在ST和MT wq中都有，只是在MT中没有那么严重。每个wq都保持着自己独立的
47 工作者池。一个MT wq只能为每个CPU提供一个执行环境，而一个ST wq则为整个
51 (MT wq)所提供的并发性水平和资源使用之间的矛盾也迫使其用户做出不必要的权衡，比
53 询PIO可以同时进行。由于MT wq并没有提供更好的并发性，需要更高层次的并
/openbmc/u-boot/board/freescale/t208xrdb/
H A Dt2080_sd_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
H A Dt2080_nand_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
H A Dt2080_spi_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
/openbmc/u-boot/board/freescale/t208xqds/
H A Dt2080_spi_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
12 #SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
H A Dt2080_sd_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
12 #SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
H A Dt2080_nand_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
12 #SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
H A Dt2081_sd_rcw.cfg4 #Core/DDR: 1533Mhz/2133MT/s
H A Dt2081_spi_rcw.cfg4 #Core/DDR: 1533Mhz/2133MT/s
H A Dt2081_nand_rcw.cfg4 #Core/DDR: 1533Mhz/2133MT/s
/openbmc/u-boot/board/freescale/ls1088a/
H A DREADME49 chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
50 with FSL refernce software is 2100MT/s
115 chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
116 with FSL refernce software is 2100MT/s
/openbmc/qemu/pc-bios/s390-ccw/
H A DMakefile24 QEMU_DGFLAGS = -MMD -MP -MT $@ -MF $(@D)/$(*F).d
68 -MMD -MP -MT $@ -MF $(@:%.o=%.d)
102 -DDHCPARCH=0x1F -MMD -MP -MT $@ -MF $(@:%.o=%.d)
/openbmc/linux/tools/build/
H A DBuild.include94 c_flags_1 = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CFLAGS) -D"BUILD_STR(s)=\#s" $(CFLAGS_$(basetarget).o) …
97 cxx_flags = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CXXFLAGS) -D"BUILD_STR(s)=\#s" $(CXXFLAGS_$(basetarget)…
102 host_c_flags = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(HOSTCFLAGS) -D"BUILD_STR(s)=\#s" $(HOSTCFLAGS_$(base…
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dt1023_sd_rcw.cfg4 #Default Core=1200MHz, DDR=1600MT/s with single source clock
H A Dt1023_spi_rcw.cfg4 #Default Core=1200MHz, DDR=1600MT/s with single source clock
H A Dt1024_sd_rcw.cfg4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
H A Dt1024_spi_rcw.cfg4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
H A Dt1024_nand_rcw.cfg4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
H A Dt1023_nand_rcw.cfg4 #Default Core=1200MHz, DDR=1600MT/s with single source clock
/openbmc/u-boot/board/freescale/t102xqds/
H A Dt1024_sd_rcw.cfg2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_spi_rcw.cfg2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_nand_rcw.cfg2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/utouch/
H A Dutouch-mtview_git.bb2 DESCRIPTION = "mtview is a small X application that shows a graphical view of your MT-enabled hardw…

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