1*ec90ac73SZhao Qiang# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz 2*ec90ac73SZhao Qiang# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz 3*ec90ac73SZhao Qiang 4*ec90ac73SZhao Qiang# PBL preamble and RCW header for T1024QDS 5*ec90ac73SZhao Qiangaa55aa55 010e0100 6*ec90ac73SZhao Qiang# Serdes protocol 0x6F 7*ec90ac73SZhao Qiang0810000e 00000000 00000000 00000000 8*ec90ac73SZhao Qiang37800001 00000012 e8104000 21000000 9*ec90ac73SZhao Qiang00000000 00000000 00000000 00030810 10*ec90ac73SZhao Qiang00000000 036c5a00 00000000 00000006 11