Searched refs:MSR_IA32_APICBASE_ENABLE (Results 1 – 16 of 16) sorted by relevance
12 ~(MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD)); in apic_disable()23 rdmsr(MSR_IA32_APICBASE) | MSR_IA32_APICBASE_ENABLE); in xapic_enable()24 } else if (!(val & MSR_IA32_APICBASE_ENABLE)) { in xapic_enable()25 wrmsr(MSR_IA32_APICBASE, val | MSR_IA32_APICBASE_ENABLE); in xapic_enable()40 MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD); in x2apic_enable()
323 if (!(val & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()329 if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()331 (val & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()337 if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()339 (val & MSR_IA32_APICBASE_ENABLE) && in apic_set_base_check()354 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); in apic_set_base()356 if (!(val & MSR_IA32_APICBASE_ENABLE)) { in apic_set_base()357 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; in apic_set_base()363 if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && in apic_set_base()364 (val & MSR_IA32_APICBASE_ENABLE)) { in apic_set_base()[all …]
75 return s->apicbase & MSR_IA32_APICBASE_ENABLE; in cpu_is_apic_enabled()257 s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; in apic_reset_common()
28 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,29 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,198 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; in kvm_apic_hw_enabled()273 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); in kvm_apic_mode()
2513 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) in kvm_free_lapic()2573 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) in kvm_lapic_set_base()2580 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { in kvm_lapic_set_base()2581 if (value & MSR_IA32_APICBASE_ENABLE) { in kvm_lapic_set_base()2595 else if (value & MSR_IA32_APICBASE_ENABLE) in kvm_lapic_set_base()2599 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { in kvm_lapic_set_base()2607 if ((value & MSR_IA32_APICBASE_ENABLE) && in kvm_lapic_set_base()2721 msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; in kvm_lapic_reset()2890 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; in kvm_create_lapic()
299 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); in __kvm_update_cpuid_runtime()
72 msr.lo |= MSR_IA32_APICBASE_ENABLE; in enable_lapic()85 msr.lo &= ~MSR_IA32_APICBASE_ENABLE; in disable_lapic()
18 #define LAPIC_X2APIC (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)
175 TEST_ASSERT(apic_base & MSR_IA32_APICBASE_ENABLE, in test_apic_id()
21 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro
59 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; in x86_cpu_apic_create()
389 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro393 (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
1220 l &= ~MSR_IA32_APICBASE_ENABLE; in disable_local_APIC()2009 if (l & MSR_IA32_APICBASE_ENABLE) in apic_verify()2032 if (!(l & MSR_IA32_APICBASE_ENABLE)) { in apic_force_enable()2035 l |= MSR_IA32_APICBASE_ENABLE | addr; in apic_force_enable()2664 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; in lapic_resume()
372 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro
785 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro
808 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro