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/openbmc/linux/Documentation/trace/
H A Devents-msr.rst2 MSR Trace Events
5 The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
13 Trace MSR reads:
17 - msr: MSR number
22 Trace MSR writes:
26 - msr: MSR number
39 to add symbolic MSR names.
/openbmc/qemu/target/ppc/
H A Dcpu.h469 FIELD(MSR, SF, MSR_SF, 1)
470 FIELD(MSR, TAG, MSR_TAG, 1)
471 FIELD(MSR, ISF, MSR_ISF, 1)
473 FIELD(MSR, HV, MSR_HV, 1)
474 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
478 FIELD(MSR, TS0, MSR_TS0, 1)
479 FIELD(MSR, TS1, MSR_TS1, 1)
480 FIELD(MSR, TS, MSR_TS0, 2)
481 FIELD(MSR, TM, MSR_TM, 1)
482 FIELD(MSR, CM, MSR_CM, 1)
[all …]
H A Dmmu-booke.c79 pr = FIELD_EX64(env->msr, MSR, PR); in mmu40x_get_physical_address()
168 FIELD_EX64(env->msr, MSR, IR) : in mmubooke_check_tlb()
169 FIELD_EX64(env->msr, MSR, DR)) != (tlb->attr & 1)) { in mmubooke_check_tlb()
174 if (FIELD_EX64(env->msr, MSR, PR)) { in mmubooke_check_tlb()
226 if (!FIELD_EX64(env->msr, MSR, CM)) { in ppcmas_tlb_check()
302 *as_out = FIELD_EX64(env->msr, MSR, DS); in mmubooke206_get_as()
303 *pr_out = FIELD_EX64(env->msr, MSR, PR); in mmubooke206_get_as()
351 as = FIELD_EX64(env->msr, MSR, IR); in mmubooke206_check_tlb()
431 as = FIELD_EX64(env->msr, MSR, IR); in booke206_update_mas_tlb_miss()
H A Dmem_helper.c35 return FIELD_EX64(env->msr, MSR, LE); in needs_byteswap()
37 return !FIELD_EX64(env->msr, MSR, LE); in needs_byteswap()
402 if (FIELD_EX64(env->msr, MSR, LE)) { \
429 if (FIELD_EX64(env->msr, MSR, LE)) { \ in LVE()
463 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
494 if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
531 (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |
535 FIELD_EX64(env->msr, MSR, PR);
H A Dexcp_helper.c468 if (FIELD_EX64(env->msr, MSR, ME)) { in powerpc_mcheck_checkstop()
525 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_40x()
636 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_6xx()
680 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_6xx()
777 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_7xx()
839 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_7xx()
927 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_74xx()
989 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_74xx()
1094 if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) { in powerpc_excp_booke()
1176 if (FIELD_EX64(env->msr, MSR, POW)) { in powerpc_excp_booke()
[all …]
/openbmc/linux/Documentation/virt/kvm/x86/
H A Dmsr.rst15 Custom MSR list
18 The current supported Custom MSR list is:
35 guaranteed to update this data at the moment of MSR write.
37 to write more than once to this MSR. Fields have the following meanings:
54 particular MSR is global.
56 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
144 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
154 This MSR falls outside the reserved KVM range and may be removed in the
157 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
166 This MSR falls outside the reserved KVM range and may be removed in the
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dfam15h_power.rst81 MaxCpuSwPwrAcc MSR C001007b
85 CpuSwPwrAcc MSR C001007a
88 by CU_PTSC MSR C0010280
98 MSR MaxCpuSwPwrAcc.
102 iii. At time x, SW reads CpuSwPwrAcc MSR and samples the PTSC.
106 iv. At time y, SW reads CpuSwPwrAcc MSR and samples the PTSC.
/openbmc/qemu/docs/tools/
H A Dqemu-vmsr-helper.rst2 QEMU virtual RAPL MSR helper
13 Implements the virtual RAPL MSR helper for QEMU.
15 Accessing the RAPL (Running Average Power Limit) MSR enables the RAPL powercap
27 system service, and you should read the QEMU manual section on "RAPL MSR
/openbmc/linux/drivers/net/hamradio/
H A Dbaycom_ser_hdx.c86 #define MSR(iobase) (iobase+6) macro
209 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ in ser12_rx()
346 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); in ser12_rx()
398 inb(MSR(dev->base_addr)); in ser12_interrupt()
432 b2 = inb(MSR(iobase)); in ser12_check_uart()
434 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
436 outb(b2, MSR(iobase)); in ser12_check_uart()
H A Dbaycom_ser_fdx.c100 #define MSR(iobase) (iobase+6) macro
262 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
296 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
350 b2 = inb(MSR(iobase)); in ser12_check_uart()
352 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
354 outb(b2, MSR(iobase)); in ser12_check_uart()
H A Dyam.c157 #define MSR(iobase) (iobase+6) macro
300 inb(MSR(iobase)); in fpga_reset()
447 rc = inb(MSR(iobase)); /* check DONE signal */ in fpga_download()
476 inb(MSR(dev->base_addr)); in yam_set_uart()
503 b2 = inb(MSR(iobase)); in yam_check_uart()
505 b3 = inb(MSR(iobase)) & 0xf0; in yam_check_uart()
507 outb(b2, MSR(iobase)); in yam_check_uart()
745 unsigned char msr = inb(MSR(dev->base_addr)); in yam_interrupt()
/openbmc/linux/Documentation/arch/x86/
H A Dsva.rst67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
86 This MSR is managed with the XSAVE feature set as "supervisor state" to
87 ensure the MSR is updated during context switch.
93 ENQCMD and program it into the new MSR to communicate the process identity to
94 platform hardware. ENQCMD uses the PASID stored in this MSR to tag requests
103 The MSR must be configured on each logical CPU before any application
105 process share the same page tables, thus the same MSR value.
119 IA32_PASID MSR lazily when a thread tries to submit a work descriptor
122 That first access will trigger a #GP fault because the IA32_PASID MSR
[all …]
H A Dpat.rst209 configurations. The PAT MSR must be updated by Linux in order to support WC
210 and WT attributes. Otherwise, the PAT MSR has the value programmed in it
211 by the firmware. Note, Xen enables WC attribute in the PAT MSR for guests.
214 MTRR PAT Call Sequence PAT State PAT MSR
237 OS PAT initializes PAT MSR with OS setting
238 BIOS PAT keeps PAT MSR with BIOS setting
/openbmc/linux/arch/x86/xen/
H A DKconfig98 bool "Always use safe MSR accesses in PV guests"
102 Use safe (not faulting) MSR access functions even if the MSR access
/openbmc/linux/Documentation/powerpc/
H A Dtransactional_memory.rst108 delivered. For future compatibility the MSR.TS field should be checked to
112 For 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS
115 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
116 bits are stored in the MSR of the second ucontext, i.e. in
257 kernel via some exception, MSR will end up as TM=0 and TS=01 (ie. TM
259 the MSR and will perform an rfid to do this. In this case rfid can
261 resulting MSR will retain TM = 0 and TS=01 from before (ie. stay in
269 if (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then
270 MSR 29:31 <- SRR1 29:31
/openbmc/qemu/docs/specs/
H A Drapl-msr.rst2 RAPL MSR support
12 Thanks to KVM's `MSR filtering <msr-filter-patch_>`__ functionality,
51 In order to update the value of the virtual MSR, a QEMU thread is created.
82 the MSR.
135 MSR support activated and the qemu-vmsr-helper. A systemd service and socket
149 - Works only on Intel host CPUs because AMD CPUs are using different MSR
/openbmc/linux/arch/sparc/include/asm/
H A Dfloppy_64.h448 #define MSR (port + 4) macro
457 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_out_byte()
472 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_sensei()
493 outb(0x80, MSR); in sun_pci_fd_reset()
531 #undef MSR
/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dspecial-register-buffer-data-sampling.rst95 IA32_MCU_OPT_CTRL MSR Definition
98 IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and
100 9]==1. This MSR is introduced through the microcode update.
H A Dtsx_async_abort.rst15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
192 and which get the new IA32_TSX_CTRL MSR through a microcode
193 update. This new MSR allows for the reliable deactivation of
220 provides a TSX control MSR. If so,
232 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl8712_cmdctrl_regdef.h14 #define MSR (RTL8712_CMDCTRL_ + 0x000C) macro
/openbmc/qemu/docs/system/i386/
H A Dhyperv.rst46 Provides so-called VP Assist page MSR to guest allowing it to work with APIC
56 Provides HV_X64_MSR_VP_INDEX (0x40000002) MSR to the guest which has Virtual
63 Provides HV_X64_MSR_VP_RUNTIME (0x40000010) MSR to the guest. The MSR keeps the
78 Enables two Hyper-V-specific clocksources available to the guest: MSR-based
80 page (enabled via MSR HV_X64_MSR_REFERENCE_TSC, 0x40000021). Both clocksources
133 Provides HV_X64_MSR_RESET (0x40000003) MSR to the guest allowing it to reset
134 itself by writing to it. Even when this MSR is enabled, it is not a recommended
231 avoid unnecessary updates to L2 MSR-Bitmap upon vmexits. While the protocol is
/openbmc/openbmc/poky/meta/lib/oeqa/runtime/cases/
H A Dparselogs-ignores-qemux86.txt2 Failed to access perfctr msr (MSR
/openbmc/qemu/contrib/systemd/
H A Dqemu-vmsr-helper.socket2 Description=Virtual RAPL MSR helper for QEMU
H A Dqemu-vmsr-helper.service2 Description=Virtual RAPL MSR Daemon for QEMU
/openbmc/linux/Documentation/virt/hyperv/
H A Dclocks.rst30 to the guest VM via a synthetic MSR. Hyper-V initialization code
31 in Linux reads this MSR to get the frequency, so it skips TSC
37 The Hyper-V synthetic system clock can be read via a synthetic MSR,

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