Searched refs:MSC0 (Results 1 – 10 of 10) sorted by relevance
23 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()37 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
17 #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ macro
980 uint32_t msc0 = __raw_readl(MSC0); in spitz_restart()983 __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); in spitz_restart()
58 clrsetbits_le32(MSC0, 0xffffffff, CONFIG_SYS_MSC0_VAL); in dram_init()
86 subdev->map.bankwidth = (MSC0 & MSC_RBW) ? 2 : 4; in sa1100_probe_subdev()90 subdev->map.bankwidth = ((MSC0 >> 16) & MSC_RBW) ? 2 : 4; in sa1100_probe_subdev()
65 writelrb(CONFIG_SYS_MSC0_VAL, MSC0); in pxa2xx_dram_init()
81 ldr r0, =MSC0
2268 #define MSC0 0x4A000008 /* Static Memory Control Register 0 */ macro2451 #define MSC0 0x48000008 /* Static Memory Control Register 0 */ macro
1921 #define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ macro1927 #define MSC0 io_p2v(0xa0000010) macro
1443 #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ macro