| /openbmc/qemu/disas/ |
| H A D | mips.c | 1240 #define MSA INSN_MSA macro
1425 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1429 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1432 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1433 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
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| /openbmc/qemu/tests/tcg/mips/user/ase/msa/ |
| H A D | README | 2 mips64el MSA-enabled CPU (I6400, I6500), using an appropriate MIPS toolchain.
14 MSA tests:
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| /openbmc/openbmc/poky/meta/recipes-devtools/gcc/gcc/ |
| H A D | 0025-gcc-testsuite-tweaks-for-mips-OE.patch | 9 Also disable MSA mips runtime extensions. For some reason qemu appears to accept the test
52 + verbose -log "No MSA avail"
120 - #error "MSA NOT AVAIL"
123 - #error "MSA NOT AVAIL FOR ISA REV < 2"
126 - #error "MSA HARD_FLOAT REQUIRED"
129 - #error "MSA 64-bit FPR REQUIRED"
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| /openbmc/linux/drivers/scsi/device_handler/ |
| H A D | Kconfig | 22 tristate "HP/COMPAQ MSA Device Handler"
25 If you have a HP/COMPAQ MSA device that requires START_STOP to
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| /openbmc/qemu/target/s390x/ |
| H A D | cpu_features.c | 244 FEAT_GROUP_INIT("msa", MSA, "Message-security-assist facility"),
|
| H A D | gen-features.c | 850 FEAT_GROUP_INITIALIZER(MSA),
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| H A D | cpu_features_def.h.inc | 39 DEF_FEAT(MSA, "msa-base", STFL, 17, "Message-security-assist facility (excluding subfunctions)")
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| /openbmc/openbmc/poky/meta/recipes-devtools/gcc/ |
| H A D | gcc-testsuite.inc | 60 # For mips64 we could set a maximal CPU (e.g. Loongson-3A4000) however they either have MSA
|
| /openbmc/qemu/target/s390x/tcg/ |
| H A D | insn-data.h.inc | 1005 /* MSA Instructions */
1006 D(0xb91e, KMAC, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMAC)
1012 D(0xb92e, KM, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KM)
1013 D(0xb92f, KMC, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KMC)
1016 D(0xb93e, KIMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KIMD)
1017 D(0xb93f, KLMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KLMD)
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| /openbmc/linux/arch/mips/ |
| H A D | Kconfig | 1524 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
2365 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2367 is enabled the kernel will support allocating & switching MSA
2369 running on CPUs which do not support MSA or that your userland will
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | msa_helper.h.inc | 2 * MIPS SIMD Architecture Module (MSA) helpers for QEMU.
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| /openbmc/linux/Documentation/virt/kvm/ |
| H A D | api.rst | 2688 if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector
2694 0x7040 0000 0003 00 <0:3> <reg:5> (128-bit MSA vector registers)
2701 MIPS MSA control registers (see KVM_REG_MIPS_MSA_{IR,CSR} above) have the
6955 This capability allows the use of the MIPS SIMD Architecture (MSA) by the guest.
6956 It allows the Config3.MSAP bit to be set to enable the use of MSA by the guest.
|