Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0 |
|
#
95539e54 |
| 31-Oct-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'mips-20221030' of https://github.com/philmd/qemu into staging
MIPS patches queue
- Convert nanoMIPS disassembler from C++ to C (Milica Lazarevic) - Consolidate VT82xx/PIIX south bridges
Merge tag 'mips-20221030' of https://github.com/philmd/qemu into staging
MIPS patches queue
- Convert nanoMIPS disassembler from C++ to C (Milica Lazarevic) - Consolidate VT82xx/PIIX south bridges (Bernhard Beschow) - Remove unused MAX_IDE_BUS definition (Zoltan Balaton) - Fix branch displacement for BEQZC/BNEZC (David Daney) - Don't set link_up for Boston's xilinx-pcie (Jiaxun Yang) - Use bootloader API to set BAR registers in Malta (Jiaxun Yang)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmNfpO8ACgkQ4+MsLN6t # wN76og/+LMuTYYRkhETZyw3v5sTAexU0kmXyf/xMZ8PLi37Al2ia3qxo70qTh34m # P2bbpCC46xzLCVY4s/84pb1lgpANNJNMIHwUni9HL4cTPPR7muKqpUOTEVh6Ghcq # Zb2+e7yTKpIgvwDcIQEzU74gDyCcJoAo4LcLRVtuXer6olQsYsmlUqr3gg+Oy5kI # zuJxOxZRoAP4H/ausGPg8oves28S3fVsw9J1x5p7vlzGt1Kx/i1XilSuGXI3H/79 # 0tgofUYkyFQRjxPLlE9OeYVwAo8gLFWwnkw/AOjHSOgGUsj/7yJXORm0ng/vQOqS # j5036BHxmhYyEVL8aJAc7fvb4/m6walsXJItThqJ/JXphdAXi17fCCn0Wf9jqGrr # io4Gm5qZI1bO/1orTaQywZTCjSi3pcuM0NxLZ/Qf7CVoXvNcddpDrSlyD3ILz9cq # XqyaKQJ3kLvWTpJ6kZknl3s4kGnnMZw+2lZlusrSjrI4QnXmgoGLiSTRPxny1qQ0 # NaqAnys0Skn0fJ002na3lJgo4mzxzN+zEzMHsbB+RZv9JB2lIwQBm+zXDFHhb9Zv # H0UFowi5lhJUjIZ5+bl4wtT2XoM4HM1YxU66a0t4SktMnKvBPCVBLUSj74Qdl1K8 # 7e2SvWB2ovNgscwek/srk1TT+yf7a6CmAraATSm0Fm/kxT5xa/Y= # =EqI/ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 31 Oct 2022 06:35:27 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-20221030' of https://github.com/philmd/qemu: (55 commits) hw/mips/malta: Use bootloader helper to set BAR registers hw/mips: Use bl_gen_kernel_jump to generate bootloaders hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register hw/mips/boston: Don't set link_up for xilinx-pcie hw/isa/piix4: Move pci_ide_create_devs() call to board code hw/isa/piix4: Add missing initialization hw/isa/Kconfig: Fix dependencies of piix4 southbridge hw/mips/malta: Reuse dev variable hw/isa/piix3: Remove unused include hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers hw/isa/piix4: Rename wrongly named method hw/isa/piix3: Prefer pci_address_space() over get_system_memory() hw/isa/piix3: Modernize reset handling hw/isa/piix3: Add size constraints to rcr_ops hw/isa/piix3: Remove extra ';' outside of functions hw/i386/pc: Create DMA controllers in south bridges disas/mips: Fix branch displacement for BEQZC and BNEZC disas/nanomips: Rename nanomips.cpp to nanomips.c disas/nanomips: Remove argument passing by ref disas/nanomips: Replace Cpp enums for C enums ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
#
a6d89b45 |
| 14-Oct-2022 |
David Daney <david.daney@fungible.com> |
disas/mips: Fix branch displacement for BEQZC and BNEZC
disas/mips.c got added in commit 6643d27ea0 ("MIPS disas support") apparently based on binutils tag 'gdb_6_1-branchpoint' [1]. Back then, MIPS
disas/mips: Fix branch displacement for BEQZC and BNEZC
disas/mips.c got added in commit 6643d27ea0 ("MIPS disas support") apparently based on binutils tag 'gdb_6_1-branchpoint' [1]. Back then, MIPSr6 was not supported (added in binutils commit 7361da2c952 during 2014 [2]).
Binutils codebase diverged so much over the last 18 years, it is not possible to simply cherry-pick their changes, so fix it BEQZC / BNEZC 21-bit signed branch displacement locally.
[1] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/mips-dis.c;hb=refs/tags/gdb_6_1-branchpoint [2] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7361da2c952
Fixes: 31837be3ee ("target-mips: add compact and CP1 branches") Signed-off-by: David Daney <david.daney@fungible.com> Reviewed-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> [PMD: Added commit description] Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221014112322.61119-1-philmd@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
show more ...
|
Revision tags: v7.0.0, v6.2.0, v6.1.0, v5.2.0, v5.0.0 |
|
#
204aa60b |
| 30-Jan-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging
MIPS queue for January 29th, 2020
# gpg: Signature made Wed 29 Jan 2020 18:29:43 GMT # gpg:
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jan-29-2020' into staging
MIPS queue for January 29th, 2020
# gpg: Signature made Wed 29 Jan 2020 18:29:43 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-jan-29-2020: target/mips: Add implementation of GINVT instruction target/mips: Amend CP0 WatchHi register implementation hw/core/loader: Let load_elf() populate a field with CPU-specific flags target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting() disas: Add a field for target-dependant data to disassemble_info target/mips: Rectify documentation on deprecating MIPS r4k machine
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
99029be1 |
| 20-Dec-2019 |
Yongbok Kim <yongbok.kim@mips.com> |
target/mips: Add implementation of GINVT instruction
Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GIN
target/mips: Add implementation of GINVT instruction
Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
show more ...
|
Revision tags: v4.2.0 |
|
#
c4e9f845 |
| 24-Apr-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-monitor-2019-04-18' into staging
Error reporting & monitor patches for 2019-04-18
# gpg: Signature made Thu 18 Apr 2019 21:40:41 BST # g
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-monitor-2019-04-18' into staging
Error reporting & monitor patches for 2019-04-18
# gpg: Signature made Thu 18 Apr 2019 21:40:41 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-error-monitor-2019-04-18: (36 commits) include: Move fprintf_function to disas/ disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h monitor: Clean up how monitor_disas() funnels output to monitor qom/cpu: Simplify how CPUClass:cpu_dump_state() prints qemu-print: New qemu_fprintf(), qemu_vfprintf() qom/cpu: Simplify how CPUClass::dump_statistics() prints target/i386: Simplify how x86_cpu_dump_local_apic_state() prints target: Clean up how the dump_mmu() print target: Simplify how the TARGET_cpu_list() print memory: Clean up how mtree_info() prints block/qapi: Clean up how we print to monitor or stdout qsp: Simplify how qsp_report() prints tcg: Simplify how dump_drift_info() prints tcg: Simplify how dump_exec_info() prints tcg: Simplify how dump_opcount_info() prints trace: Simplify how st_print_trace_file_status() prints include: Include fprintf-fn.h only where needed monitor: Simplify how -device/device_add print help char-pty: Print "char device redirected" message to stdout char: Make -chardev help print to stdout ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: v4.0.0 |
|
#
3979fca4 |
| 17-Apr-2019 |
Markus Armbruster <armbru@redhat.com> |
disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h
Commit dc99065b5f9 (v0.1.0) added dis-asm.h from binutils.
Commit 43d4145a986 (v0.1.5) inlined bfd.h into dis-asm.h to remove the d
disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h
Commit dc99065b5f9 (v0.1.0) added dis-asm.h from binutils.
Commit 43d4145a986 (v0.1.5) inlined bfd.h into dis-asm.h to remove the dependency on binutils.
Commit 76cad71136b (v1.4.0) moved dis-asm.h to include/disas/bfd.h. The new name is confusing when you try to match against (pre GPLv3+) binutils. Rename it back. Keep it in the same directory, of course.
Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-17-armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
show more ...
|
Revision tags: v4.0.0-rc1, v4.0.0-rc0, v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, libfdt-20181002, ppc-for-3.1-20180925, ppc-for-3.1-20180907, ppc-for-3.1-20180821, v3.0.0, v3.0.0-rc4, v2.12.1, ppc-for-3.0-20180801, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, ppc-for-3.0-20180716, v3.0.0-rc0, ppc-for-3.0-20180709, ppc-for-3.0-20180703, v2.11.2, ppc-for-3.0-20180622, ppc-for-3.0-20180618, ppc-for-3.0-20180612, ppc-for-2.13-20180504, ppc-for-2.13-20180427, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, ppc-for-2.12-20180410, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, ppc-for-2.12-20180319, ppc-for-2.12-20180315, ppc-for-2.12-20180306, ppc-for-2.12-20180302, ppc-for-2.12-20180216, v2.11.1, ppc-for-2.12-20180212, ppc-for-2.12-20180129, ppc-for-2.12-20180121, ppc-for-2.12-20180119, ppc-for-2.12-20180117, ppc-for-2.12-20180111, ppc-for-2.12-20180108, ppc-for-2.12-20180103, ppc-for-2.12-20171219, v2.10.2, ppc-for-2.12-20171215, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, ppc-for-2.11-20171205, ppc-for-2.11-20171204, v2.11.0-rc3, ppc-for-2.11-20171127, ppc-for-2.11-20171122, v2.11.0-rc2, ppc-for-2.11-20171120, v2.11.0-rc1, ppc-for-2.11-20171114, ppc-for-2.11-20171108, v2.11.0-rc0, ppc-for-2.11-20171017, v2.10.1, ppc-for-2.11-20170927, ppc-for-2.11-20170915, ppc-for-2.11-20170908, v2.9.1, v2.10.0, v2.10.0-rc4, ppc-for-2.10-20170823, ppc-for-2.10-20170822, v2.10.0-rc3, ppc-for-2.10-20170809, v2.10.0-rc2, v2.10.0-rc1, ppc-for-2.10-20170731, v2.10.0-rc0, ppc-for-2.10-20170725, ppc-for-2.10-20170717, ppc-for-2.10-20170714, ppc-for-2.10-20170711, ppc-for-2.10-20170630, ppc-for-2.10-20170609, ppc-for-2.10-20170606, ppc-for-2.10-20170525, ppc-for-2.10-20170511, ppc-for-2.10-20170510, ppc-for-2.10-20170426, ppc-for-2.10-20170424, v2.8.1.1, v2.9.0, v2.9.0-rc5, v2.9.0-rc4, v2.9.0-rc3, ppc-for-2.9-20170403, v2.8.1, ppc-for-2.9-20170329, v2.9.0-rc2, ppc-for-2.9-20170323, v2.9.0-rc1, v2.9.0-rc0, ppc-for-2.9-20170314, ppc-for-2.9-20170306, submodule-update-20170303, ppc-for-2.9-20170303, ppc-for-2.9-20170301, ppc-for-2.9-20170222, isa-cleanup-20170206, ppc-for-2.9-20170202, ppc-for-2.9-20170112, master-20170112, v2.7.1, v2.8.0, v2.8.0-rc4, v2.8.0-rc3, ppc-for-2.8-20161201, v2.8.0-rc2, ppc-for-2.8-20161123, v2.8.0-rc1, isa-cleanup-20161118, qemu-kvm-1.5.3-127.el7, v2.8.0-rc0, ppc-for-2.8-20161115, qemu-kvm-1.5.3-126.el7_3.1, qemu-kvm-0.12.1.2-2.496.el6, ppc-for-2.8-20161028, qemu-kvm-0.12.1.2-2.495.el6, ppc-for-2.8-20161026, ppc-for-2.8-20161017, qemu-kvm-rhev-2.3.0-31.el7_2.23, ppc-for-2.7-20161013, qemu-kvm-1.5.3-105.el7_2.10, ppc-for-2.8-20161006, qemu-kvm-1.5.3-105.el7_2.9, v2.6.2, RHELSA-7.3_qemu-kvm-rhev, qemu-kvm-rhev-2.6.0-28.el7, RHEL-7.3_qemu-kvm-rhev, qemu-kvm-rhev-2.6.0-27.el7, ppc-for-2.8-20160923, qemu-kvm-0.12.1.2-2.494.el6, ppc-for-2.8-20160922, RHEL-7.3_qemu-kvm, qemu-kvm-1.5.3-126.el7, qemu-kvm-rhev-2.6.0-26.el7, vfio-fixes-20160915.0, qemu-kvm-1.5.3-125.el7, qemu-kvm-rhev-2.3.0-31.el7_2.22, qemu-kvm-rhev-2.6.0-25.el7, qemu-kvm-1.5.3-124.el7, qemu-kvm-rhev-2.6.0-24.el7, qemu-kvm-1.5.3-123.el7, qemu-kvm-0.12.1.2-2.415.el6_5.16, ppc-for-2.8-20160907, qemu-kvm-rhev-2.6.0-23.el7, ppc-for-2.8-20160906, v2.7.0, RHEL-7.3-qemu-guest-agent, qemu-guest-agent-2.5.0-3.el7, v2.7.0-rc5, qemu-kvm-1.5.3-122.el7, qemu-kvm-rhev-2.6.0-22.el7, v2.7.0-rc4, v2.6.1, v2.7.0-rc3, qemu-kvm-rhev-2.6.0-21.el7, qemu-kvm-1.5.3-105.el7_2.8, ppc-for-2.7-20160815, qemu-kvm-rhev-2.6.0-20.el7, ppc-for-2.7-20160810, v2.7.0-rc2, ppc-for-2.7-20160808, qemu-kvm-rhev-2.6.0-19.el7, ppc-for-2.7-20160803, qemu-kvm-rhev-2.6.0-18.el7, qemu-kvm-1.5.3-105.el7_2.7, qemu-kvm-rhev-2.3.0-31.el7_2.21, qemu-kvm-1.5.3-121.el7, v2.7.0-rc1, qemu-kvm-rhev-2.6.0-17.el7, qemu-kvm-1.5.3-120.el7, ppc-for-2.7-20160729, qemu-kvm-0.12.1.2-2.493.el6, qemu-kvm-1.5.3-105.el7_2.6, qemu-kvm-0.12.1.2-2.491.el6_8.3, qemu-kvm-rhev-2.3.0-31.el7_2.20, qemu-kvm-1.5.3-119.el7, qemu-kvm-rhev-2.6.0-16.el7, ppc-for-2.7-20160726, v2.7.0-rc0, qemu-kvm-rhev-2.6.0-15.el7, qemu-kvm-rhev-2.3.0-31.el7_2.19 |
|
#
0c1b58f2 |
| 19-Jul-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
# gpg: Signature made Mon 18 Jul 2016 22:59:55 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
# gpg: Signature made Mon 18 Jul 2016 22:59:55 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/tracing-pull-request: trace: Add QAPI/QMP interfaces to query and control per-vCPU tracing state trace: Allow event name pattern in "info trace-events" trace: Conditionally trace events based on their per-vCPU state trace: Add per-vCPU tracing states for events with the 'vcpu' property trace: Cosmetic changes on fast-path tracing disas: Remove unused macro '_' trace: Identify events with the 'vcpu' property trace: [bsd-user] Commandline arguments to control tracing trace: [linux-user] Commandline arguments to control tracing
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: qemu-kvm-rhev-2.6.0-14.el7, qemu-kvm-1.5.3-118.el7, vfio-update-20160718.0, ppc-for-2.7-20160718, qemu-kvm-1.5.3-117.el7, qemu-kvm-rhev-2.6.0-13.el7 |
|
#
ca66f1a1 |
| 11-Jul-2016 |
Lluís Vilanova <vilanova@ac.upc.edu> |
disas: Remove unused macro '_'
Eliminates a future compilation error when UI code includes the tracing headers (indirectly pulling "disas/bfd.h" through "qom/cpu.h") and GLib's i18n '_' macro.
Sign
disas: Remove unused macro '_'
Eliminates a future compilation error when UI code includes the tracing headers (indirectly pulling "disas/bfd.h" through "qom/cpu.h") and GLib's i18n '_' macro.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
Revision tags: qemu-kvm-rhev-2.6.0-12.el7, qemu-kvm-rhev-2.3.0-31.el7_2.18, ppc-for-2.7-20160705, qemu-kvm-rhev-2.6.0-11.el7, qemu-kvm-1.5.3-105.el7_2.5, ppc-for-2.7-20160701, vfio-update-20160630.0, qemu-kvm-0.12.1.2-2.492.el6, qemu-kvm-rhev-2.6.0-10.el7, qemu-kvm-rhev-2.3.0-31.el7_2.17, qemu-kvm-1.5.3-116.el7, ppc-for-2.7-20160627, qemu-kvm-rhev-2.6.0-9.el7, ppc-for-2.7-20160623, qemu-kvm-0.12.1.2-2.491.el6_8.2, qemu-kvm-rhev-2.6.0-8.el7, qemu-kvm-1.5.3-115.el7, ppc-for-2.7-20160617, qemu-kvm-rhev-2.3.0-31.el7_2.16, qemu-kvm-rhev-2.6.0-7.el7, qemu-kvm-rhev-2.6.0-6.el7, qemu-kvm-1.5.3-114.el7, qemu-guest-agent-2.5.0-2.el7, ppc-for-2.7-20160614, ppc-for-2.7-20160607, qemu-kvm-rhev-2.3.0-31.el7_2.15, qemu-kvm-rhev-2.6.0-5.el7, ppc-for-2.7-20160531, qemu-kvm-1.5.3-113.el7, ppc-for-2.7-20160527, vfio-update-20160526.1, maintainers-for-peter, qemu-kvm-rhev-2.6.0-4.el7, qemu-kvm-rhev-2.6.0-3.el7, qemu-kvm-rhev-2.1.2-23.el7_1.12, qemu-kvm-rhev-2.6.0-2.el7, qemu-kvm-rhev-2.3.0-31.el7_2.14, qemu-kvm-1.5.3-112.el7, qemu-kvm-rhev-2.6.0-1.el7, v2.6.0, v2.5.1.1, v2.6.0-rc5, qemu-kvm-1.5.3-111.el7, qemu-kvm-1.5.3-110.el7, qemu-kvm-0.12.1.2-2.479.el6_7.5, qemu-kvm-0.12.1.2-2.491.el6_8.1, qemu-kvm-rhev-2.3.0-31.el7_2.13, v2.6.0-rc4, ppc-for-2.6-20160426, ppc-for-2.6-20160423, v2.6.0-rc3, ppc-for-2.6-20160419, ppc-for-2.6-20160418, v2.6.0-rc2, qemu-kvm-rhev-2.3.0-31.el7_2.12, ppc-for-2.6-20160408, qemu-kvm-rhev-2.3.0-31.el7_2.11, v2.6.0-rc1, ppc-for-2.6-20160405, openbmc-20160404-1, qemu-kvm-rhev-2.5.0-4.el7, v2.6.0-rc0, qemu-kvm-0.12.1.2-2.491.el6, v2.5.1, vfio-update-20160328.0, ppc-for-2.6-20160324, qemu-kvm-rhev-2.5.0-3.el7, vfio-ddw-20160322, machine-pull-request, ppc-for-2.6-20160316, qemu-kvm-rhev-2.3.0-31.el7_2.10, qemu-kvm-1.5.3-109.el7, qemu-kvm-rhev-2.3.0-31.el7_2.9, vfio-update-20160310.2, vfio-update-20160311.0, qemu-kvm-rhev-2.5.0-2.el7, qemu-kvm-0.12.1.2-2.490.el6, ppc-for-2.6-20160229 |
|
#
4d1e324b |
| 26-Feb-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into staging
MIPS patches 2016-02-26
Changes: * support for FPU and MSA in KVM guest * support for R6 Virtual Processors
# gpg: Sig
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160226' into staging
MIPS patches 2016-02-26
Changes: * support for FPU and MSA in KVM guest * support for R6 Virtual Processors
# gpg: Signature made Fri 26 Feb 2016 11:07:37 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
* remotes/lalrae/tags/mips-20160226: target-mips: implement R6 multi-threading mips/kvm: Support MSA in MIPS KVM guests mips/kvm: Support FPU in MIPS KVM guests mips/kvm: Support signed 64-bit KVM registers mips/kvm: Support unsigned KVM registers mips/kvm: Implement Config CP0 registers mips/kvm: Implement PRid CP0 register mips/kvm: Remove a couple of noisy DPRINTFs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: ppc-for-2.6-20160225, qemu-kvm-rhev-2.3.0-31.el7_2.8, qemu-slof-20160223, vfio-update-20160219.1, qemu-kvm-0.12.1.2-2.489.el6, ppc-for-2.6-20160218, qemu-kvm-1.5.3-108.el7 |
|
#
01bc435b |
| 03-Feb-2016 |
Yongbok Kim <yongbok.kim@imgtec.com> |
target-mips: implement R6 multi-threading
MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virt
target-mips: implement R6 multi-threading
MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
show more ...
|
Revision tags: ppc-for-2.6-20160201, qemu-kvm-0.12.1.2-2.487.el6, ppc-for-2.6-20160129, qemu-kvm-0.12.1.2-2.479.el6_7.4, qemu-kvm-0.12.1.2-2.486.el6 |
|
#
6ee06cc3 |
| 25-Jan-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160125' into staging
MIPS patches 2016-01-25
Changes: * fixes and includes clean-up
# gpg: Signature made Mon 25 Jan 2016 09:29:51 GMT usin
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160125' into staging
MIPS patches 2016-01-25
Changes: * fixes and includes clean-up
# gpg: Signature made Mon 25 Jan 2016 09:29:51 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
* remotes/lalrae/tags/mips-20160125: mips: Clean up includes target-mips: Fix ALIGN instruction when bp=0 target-mips: silence NaNs for cvt.s.d and cvt.d.s target-mips/cpu.h: Fix spell error
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: ppc-for-2.6-20160125, qemu-kvm-0.12.1.2-2.485.el6, qemu-kvm-rhev-2.3.0-31.el7_2.7, qemu-kvm-1.5.3-105.el7_2.3, qemu-kvm-1.5.3-105.el7_2.2, qemu-kvm-1.5.3-107.el7, vfio-update-20160119.0, qemu-kvm-0.12.1.2-2.484.el6 |
|
#
c684822a |
| 18-Jan-2016 |
Peter Maydell <peter.maydell@linaro.org> |
mips: Clean up includes
Clean up includes so that osdep.h is included first and headers which it implies are not included manually.
This commit was created with scripts/clean-includes.
Signed-off-
mips: Clean up includes
Clean up includes so that osdep.h is included first and headers which it implies are not included manually.
This commit was created with scripts/clean-includes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
show more ...
|
Revision tags: qom-devices-for-peter, qemu-kvm-rhev-2.3.0-31.el7_2.6, qemu-kvm-1.5.3-106.el7, qemu-guest-agent-2.5.0-1.el7, qemu-kvm-rhev-2.5.0-1.el7, ppc-for-2.6-20160111, qemu-kvm-0.12.1.2-2.483.el6, x86-next-pull-request, qemu-kvm-0.12.1.2-2.479.el6_7.3, v2.5.0, qemu-kvm-0.12.1.2-2.482.el6, v2.5.0-rc4, qemu-kvm-rhev-2.3.0-31.el7_2.5, v2.5.0-rc3, ppc-for-2.5-20151204, qemu-kvm-rhev-2.3.0-31.el7_2.4, qemu-kvm-rhev-2.3.0-31.el7_2_2.4, ppc-for-2.5-20151130, v2.5.0-rc2, v2.5.0-rc1, qemu-kvm-rhev-2.3.0-31.el7_2.3, qemu-kvm-rhev-2.3.0-31.el7_2.2, qemu-kvm-1.5.3-105.el7_2.1, qemu-kvm-rhev-2.1.2-23.el7_1.11, v2.5.0-rc0, ppc-next-20151112, ppc-next-20151111, vfio-update-20151110.0, qemu-kvm-rhev-2.3.0-31.el7_2.1, v2.4.1, ppc-next-20151023 |
|
#
6a6739de |
| 22-Oct-2015 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151021' into staging
Collected tcg backend patches
# gpg: Signature made Wed 21 Oct 2015 22:34:28 BST using RSA key ID 4DD0279B # gpg: Good
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151021' into staging
Collected tcg backend patches
# gpg: Signature made Wed 21 Oct 2015 22:34:28 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>"
* remotes/rth/tags/pull-tcg-20151021: cpu-exec: Add "nochain" debug flag tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ tcg/mips: Support r6 multiply/divide encodings tcg/mips: Support r6 JR encoding tcg/mips: Add use_mips32r6_instructions definition disas/mips: Add R6 jr/jr.hb to disassembler tcg-opc.h: Simplify insn_start def tcg/ppc: Prefer mask over andi. tcg/ppc: Revise goto_tb implementation tcg/ppc: Adjust exit_tb for change in prologue placement
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: qom-cpu-for-peter, qemu-kvm-1.5.3-86.el7_1.8, RHEL-7.2_qemu-kvm, qemu-kvm-1.5.3-105.el7, RHEL-7.2_qemu-kvm-rhev, qemu-kvm-rhev-2.3.0-31.el7, qemu-kvm-rhev-2.3.0-30.el7, qemu-kvm-rhev-2.1.2-23.el7_1_1.10, qemu-kvm-1.5.3-86.el7_1.7, ppc-next-20151009, qemu-kvm-rhev-2.3.0-29.el7, vfio-update-20151005.0, vfio-update-20151007.0, qemu-kvm-rhev-2.3.0-28.el7 |
|
#
d76f3653 |
| 02-Oct-2015 |
James Hogan <james.hogan@imgtec.com> |
disas/mips: Add R6 jr/jr.hb to disassembler
MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these encodings to the MIPS disassembly table.
Reviewed-by: Aurelien Jarno <aurelien@a
disas/mips: Add R6 jr/jr.hb to disassembler
MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these encodings to the MIPS disassembly table.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1443788657-14537-3-git-send-email-james.hogan@imgtec.com>
show more ...
|
Revision tags: qemu-kvm-rhev-2.3.0-27.el7, qemu-kvm-0.12.1.2-2.479.el6_7.2, qemu-kvm-0.12.1.2-2.481.el6, qemu-kvm-rhev-2.3.0-26.el7, vfio-update-20150925.0, vfio-update-20150923.0, qemu-kvm-rhev-2.3.0-25.el7, qemu-kvm-1.5.3-104.el7, spapr-next-20150923, v2.4.0.1, spapr-next-20150921, qemu-kvm-rhev-2.3.0-24.el7, spapr-next-20150916, qemu-kvm-rhev-2.3.0-23.el7, RHEL-7.2_qemu-guest-agent, qemu-guest-agent-2.3.0-4.el7, qemu-kvm-1.5.3-103.el7, qemu-kvm-rhev-2.3.0-22.el7, qemu-kvm-1.5.3-102.el7, spapr-next-20150903, qemu-kvm-rhev-2.1.2-23.el7_1.9, qemu-kvm-rhev-2.3.0-21.el7, qemu-kvm-rhev-2.3.0-20.el7, qemu-guest-agent-2.3.0-3.el7, qemu-kvm-rhev-2.3.0-19.el7, qemu-kvm-1.5.3-101.el7, qemu-kvm-rhev-2.3.0-18.el7, qemu-kvm-rhev-2.3.0-17.el7, v2.4.0, v2.3.1, qemu-kvm-1.5.3-100.el7, qemu-kvm-rhev-2.3.0-16.el7, qemu-kvm-0.12.1.2-2.479.el6_7.1, qemu-kvm-0.12.1.2-2.480.el6, qemu-kvm-rhev-2.1.2-23.el7_1.8, qemu-kvm-1.5.3-86.el7_1.6, qemu-kvm-1.5.3-99.el7, v2.4.0-rc4, qemu-kvm-rhev-2.3.0-15.el7, qemu-kvm-rhev-2.1.2-23.el7_1_1.7, qemu-kvm-rhev-2.3.0-14.el7, v2.4.0-rc3, qemu-kvm-1.5.3-98.el7, qemu-kvm-rhev-2.3.0-13.el7, vfio-fixes-20150723.0, v2.4.0-rc2, qemu-kvm-1.5.3-86.el7_1.5, qemu-kvm-rhev-2.1.2-23.el7_1.6, qemu-kvm-rhev-2.1.2-23.el7_1.5, qemu-kvm-rhev-2.3.0-12.el7, qemu-kvm-1.5.3-86.el7_1.4, qemu-kvm-1.5.3-97.el7, qemu-kvm-rhev-2.3.0-11.el7, qemu-kvm-1.5.3-96.el7, v2.4.0-rc1 |
|
#
2d5ee9e7 |
| 16-Jul-2015 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging
MIPS patches 2015-07-16
Changes: * bug fixes
# gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29D
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging
MIPS patches 2015-07-16
Changes: * bug fixes
# gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20150716: target-mips: fix page fault address for LWL/LWR/LDL/LDR linux-user: Fix MIPS N64 trap and break instruction bug target-mips: fix resource leak reported by Coverity target-mips: fix logically dead code reported by Coverity target-mips: correct DERET instruction target-mips: fix ASID synchronisation for MIPS MT disas/mips: fix disassembling R6 instructions target-mips: fix to clear MSACSR.Cause target-mips: fix MIPS64R6-generic configuration
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: qemu-kvm-rhev-2.3.0-10.el7, qemu-guest-agent-2.3.0-2.el7, v2.4.0-rc0, qemu-kvm-rhev-2.3.0-9.el7, qemu-kvm-rhev-2.3.0-8.el7, qemu-kvm-1.5.3-95.el7, vfio-update-20150706.0, qemu-kvm-rhev-2.3.0-7.el7, spapr-next-20150702 |
|
#
6b9c26fb |
| 30-Jun-2015 |
Yongbok Kim <yongbok.kim@imgtec.com> |
disas/mips: fix disassembling R6 instructions
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF and CACHE instructions have 9 bits offsets.
Signed-off-by: Yongbok Kim <yongbok.kim@i
disas/mips: fix disassembling R6 instructions
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF and CACHE instructions have 9 bits offsets.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
show more ...
|
Revision tags: qemu-kvm-rhev-2.3.0-6.el7, qemu-kvm-1.5.3-94.el7, for_autotest, for_autotest_next, for_upstream, qemu-kvm-rhev-2.1.2-23.el7_1.4, qemu-kvm-rhev-2.1.2-23.el7_1_1.3, qemu-kvm-rhev-2.3.0-5.el7, qemu-kvm-1.5.3-86.el7_1.3, qemu-kvm-1.5.3-93.el7, RHEL-6.7, qemu-kvm-0.12.1.2-2.479.el6, qemu-kvm-rhev-2.3.0-4.el7, qemu-kvm-rhev-2.3.0-3.el7, qemu-kvm-1.5.3-92.el7, qemu-kvm-1.5.3-91.el7 |
|
#
4cb618ab |
| 12-Jun-2015 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150612' into staging
MIPS patches 2015-06-12
Changes: * improve dp8393x network card and rc4030 chipset emulation * support misaligned R6 an
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150612' into staging
MIPS patches 2015-06-12
Changes: * improve dp8393x network card and rc4030 chipset emulation * support misaligned R6 and MSA memory accesses * support MIPS eXtended and Large Physical Addressing * add Config5.FRE bit and ERETNC instruction (Config5.LLB) * support ememsize on MALTA
# gpg: Signature made Fri Jun 12 09:38:11 2015 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20150612: (29 commits) target-mips: enable XPA and LPA features target-mips: remove misleading comments in translate_init.c target-mips: add MTHC0 and MFHC0 instructions target-mips: add CP0.PageGrain.ELPA support target-mips: support Page Frame Number Extension field target-mips: extend selected CP0 registers to 64-bits in MIPS32 target-mips: correct MFC0 for CP0.EntryLo in MIPS64 net/dp8393x: fix hardware reset net/dp8393x: correctly reset in_use field net/dp8393x: add load/save support net/dp8393x: add PROM to store MAC address net/dp8393x: QOM'ify net/dp8393x: use dp8393x_ prefix for all functions net/dp8393x: do not use old_mmio accesses net/dp8393x: always calculate proper checksums dma/rc4030: convert to QOM dma/rc4030: use trace events instead of custom logging dma/rc4030: document register at offset 0x210 dma/rc4030: do not use old_mmio accesses dma/rc4030: use AddressSpace and address_space_rw in users ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: vfio-update-20150609.0, vfio-update-20150608.0, qemu-kvm-1.5.3-90.el7, qemu-kvm-0.12.1.2-2.478.el6, x86-pull-request, qemu-kvm-0.12.1.2-2.448.el6_6.4, qemu-kvm-0.12.1.2-2.477.el6, qemu-kvm-rhev-2.3.0-2.el7, qemu-kvm-1.5.3-89.el7, qemu-kvm-0.12.1.2-2.476.el6, spapr-dev-staging, qemu-kvm-0.12.1.2-2.415.el6_5.15, signed-s390-for-upstream-for, qemu-kvm-1.5.3-86.el7_1.2, qemu-kvm-rhev-2.1.2-23.el7_1.3, qemu-kvm-rhev-0.12.1.2-2.448.el6_6.3, qemu-kvm-0.12.1.2-2.475.el6, qemu-kvm-0.12.1.2-2.474.el6, qemu-kvm-1.5.3-88.el7, qemu-kvm-0.12.1.2-2.473.el6, spapr-next-20150501, qemu-kvm-0.12.1.2-2.472.el6, qemu-kvm-0.12.1.2-2.471.el6, vfio-update-20150428.0, qemu-guest-agent-2.3.0-1.el7, qemu-kvm-rhev-2.3.0-1.el7, numa-pull-request, qemu-kvm-0.12.1.2-2.470.el6, qemu-kvm-0.12.1.2-2.469.el6, qemu-2.3.0, v2.3.0, qemu-kvm-0.12.1.2-2.468.el6, qemu-kvm-0.12.1.2-2.467.el6, qemu-kvm-rhev-2.2.0-9.el7, qemu-kvm-rhev-2.1.2-23.el7_1.2, qemu-kvm-rhev-2.1.2-23.el7_1_1.2, qemu-2.3.0-rc4, v2.3.0-rc4, qemu-kvm-0.12.1.2-2.466.el6, v2.3.0-rc3, qemu-kvm-0.12.1.2-2.465.el6, qemu-kvm-0.12.1.2-2.448.el6_6.2, qemu-kvm-0.12.1.2-2.464.el6, qemu-kvm-0.12.1.2-2.463.el6, qemu-2.3.0-rc2, v2.3.0-rc2, qtest-for-2.3, qemu-kvm-0.12.1.2-2.448.el6_6.1, qemu-kvm-0.12.1.2-2.462.el6, qemu-kvm-0.12.1.2-2.460.el6, v2.3.0-rc1, qemu-kvm-0.12.1.2-2.459.el6, work/numa-verify-cpus-pull-request, qemu-kvm-rhev-2.2.0-8.el7, qemu-kvm-1.5.3-87.el7, qemu-2.3.0-rc0, v2.3.0-rc0, qemu-kvm-0.12.1.2-2.458.el6, v2.2.1, qemu-kvm-rhev-2.2.0-7.el7, qemu-kvm-0.12.1.2-2.457.el6, qemu-kvm-1.5.3-86.el7_1.1, qemu-kvm-0.12.1.2-2.456.el6, qemu-kvm-0.12.1.2-2.455.el6, vfio-update-20150302.0, qemu-kvm-rhev-2.2.0-6.el7, for_upstream_rebased, qemu-kvm-0.12.1.2-2.454.el6, numa-next-pull-request, qemu-kvm-rhev-2.1.2-23.el7_1.1, qemu-kvm-1.5.3-60.el7_0.12, qemu-kvm-0.12.1.2-2.453.el6, qga-pull-2015-02-16-v2-tag, qemu-kvm-rhev-2.2.0-5.el7, vfio-update-20150210.0, vfio-update-20150209.0, qemu-kvm-rhev-2.2.0-4.el7, vfio-update-20150204.0, qemu-kvm-0.12.1.2-2.452.el6, RHEL-7.1_qemu-kvm-rhev, qemu-kvm-rhev-2.1.2-23.el7, qemu-kvm-rhev-2.1.2-22.el7, RHEL-7.1_qemu-kvm, qemu-kvm-1.5.3-86.el7, qemu-kvm-rhev-2.1.2-21.el7, qemu-kvm-rhev-2.2.0-3.el7, v2.1.3, qemu-kvm-rhev-2.1.2-20.el7, qemu-kvm-0.12.1.2-2.451.el6, qemu-kvm-rhev-2.2.0-2.el7, qemu-kvm-rhev-2.1.2-19.el7, qemu-kvm-0.12.1.2-2.450.el6, vfio-update-20150109.0, qemu-kvm-rhev-2.1.2-18.el7, qemu-kvm-1.5.3-85.el7, vfio-update-20141222.0, qemu-kvm-0.12.1.2-2.449.el6, qemu-kvm-rhev-2.1.2-17.el7, qemu-kvm-1.5.3-84.el7, qemu-2.2.0, v2.2.0, qemu-kvm-rhev-2.1.2-16.el7, v2.2.0-rc5, qemu-kvm-rhev-2.1.2-15.el7, qemu-2.2.0-rc4, v2.2.0-rc4, qemu-kvm-rhev-2.1.2-14.el7, qemu-kvm-1.5.3-83.el7, v2.2.0-rc3, qemu-kvm-rhev-2.1.2-13.el7, qemu-kvm-1.5.3-82.el7, qemu-kvm-1.5.3-60.el7_0.11, qemu-kvm-rhev-2.1.2-12.el7, qemu-kvm-1.5.3-81.el7, qemu-kvm-rhev-2.1.2-11.el7, qemu-kvm-1.5.3-80.el7, qemu-kvm-rhev-2.1.2-10.el7, qemu-kvm-rhev-2.1.2-9.el7, v2.2.0-rc2, qemu-kvm-rhev-2.1.2-8.el7, qemu-kvm-1.5.3-79.el7, v2.2.0-rc1, qemu-kvm-1.5.3-78.el7, qemu-kvm-rhev-2.1.2-7.el7, v2.2.0-rc0, qemu-kvm-rhev-2.1.2-6.el7, qemu-kvm-rhev-2.1.2-5.el7, qemu-kvm-1.5.3-77.el7, qga-pull-2014-10-22-tag, qemu-kvm-1.5.3-76.el7, RHEL-7.1_qemu-guest-agent, qemu-guest-agent-2.1.0-4.el7, qemu-kvm-rhev-2.1.2-4.el7, qemu-kvm-rhev-2.1.2-3.el7, qemu-kvm-rhev-2.1.2-2.el7, qemu-kvm-1.5.3-75.el7, for-upstream, qemu-kvm-1.5.3-60.el7_0.10, qemu-kvm-1.5.3-74.el7, qemu-kvm-0.12.1.2-2.448.el6, qemu-kvm-2.1.2-1.el7, qemu-2.1.2, v2.1.2, qemu-kvm-rhev-2.1.0-5.el7, qemu-kvm-0.12.1.2-2.447.el6, qemu-kvm-1.5.3-60.el7_0.9, qemu-kvm-1.5.3-73.el7, vfio-pci-for-qemu-20140923.0, qemu-kvm-1.5.3-60.el7_0.8, qemu-kvm-1.5.3-72.el7, qemu-kvm-1.5.3-71.el7, vp-2.1.0-v1, vp-2.1.0-v2, vp-2.1.0-v3, qemu-kvm-rhev-2.1.0-4.el7, qemu-kvm-0.12.1.2-2.446.el6, qemu-kvm-1.5.3-70.el7 |
|
#
5204ea79 |
| 11-Sep-2014 |
Leon Alrae <leon.alrae@imgtec.com> |
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers.
In MIPS64, when CP0 destinat
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers.
In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
show more ...
|
#
ce9782f4 |
| 04-Jun-2015 |
Leon Alrae <leon.alrae@imgtec.com> |
target-mips: add ERETNC instruction and Config5.LLB bit
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed
target-mips: add ERETNC instruction and Config5.LLB bit
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail.
Presence of ERETNC is denoted by the Config5.LLB.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
show more ...
|
#
84afc4dd |
| 17-Dec-2014 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141216' into staging
* remotes/lalrae/tags/mips-20141216: (30 commits) target-mips: remove excp_names[] from linux-user as it is unused d
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141216' into staging
* remotes/lalrae/tags/mips-20141216: (30 commits) target-mips: remove excp_names[] from linux-user as it is unused disas/mips: disable unused mips16_to_32_reg_map[] disas/mips: remove unused mips_msa_control_names_numeric[32] target-mips: convert single case switch into if statement target-mips: Fix DisasContext's ulri member initialization target-mips: Use local float status pointer across MSA macros target-mips: Add missing calls to synchronise SoftFloat status linux-user: Use the 5KEf processor for 64-bit emulation target-mips: Also apply the CP0.Status mask to MTTC0 target-mips: gdbstub: Clean up FPU register handling target-mips: Correct 32-bit address space wrapping target-mips: Tighten ISA level checks target-mips: Fix CP0.Config3.ISAOnExc write accesses target-mips: Output CP0.Config2-5 in the register dump target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP target-mips: Correct the writes to Status and Cause registers via gdbstub target-mips: Correct the handling of writes to CP0.Status for MIPSr6 target-mips: Correct MIPS16/microMIPS branch size calculation target-mips: Restore the order of helpers target-mips: Remove unused `FLOAT_OP' macro ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
8ef39152 |
| 12-Dec-2014 |
Leon Alrae <leon.alrae@imgtec.com> |
disas/mips: disable unused mips16_to_32_reg_map[]
This array is used by print_mips16_insn_arg() which is guarded by #if 0. Therefore doing the same with the array as it generates clang warnings.
Si
disas/mips: disable unused mips16_to_32_reg_map[]
This array is used by print_mips16_insn_arg() which is guarded by #if 0. Therefore doing the same with the array as it generates clang warnings.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
show more ...
|
#
8e5f7570 |
| 10-Dec-2014 |
Leon Alrae <leon.alrae@imgtec.com> |
disas/mips: remove unused mips_msa_control_names_numeric[32]
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
|
#
d7806155 |
| 03-Nov-2014 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141103' into staging
* remotes/lalrae/tags/mips-20141103: (34 commits) target-mips: add MSA support to mips32r5-generic disas/mips.c: dis
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141103' into staging
* remotes/lalrae/tags/mips-20141103: (34 commits) target-mips: add MSA support to mips32r5-generic disas/mips.c: disassemble MSA instructions target-mips: add MSA MI10 format instructions target-mips: add MSA 2RF format instructions target-mips: add MSA VEC/2R format instructions target-mips: add MSA 3RF format instructions target-mips: add MSA ELM format instructions target-mips: add MSA 3R format instructions target-mips: add MSA BIT format instructions target-mips: add MSA I5 format instruction target-mips: add MSA I8 format instructions target-mips: add MSA branch instructions target-mips: add msa_helper.c target-mips: add msa_reset(), global msa register target-mips: add MSA opcode enum target-mips: stop translation after ctc1 target-mips: remove duplicated mips/ieee mapping function target-mips: add MSA exceptions target-mips: add MSA defines and data structure target-mips: enable features in MIPS64R6-generic CPU ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
ed8a933f |
| 01-Nov-2014 |
Yongbok Kim <yongbok.kim@imgtec.com> |
disas/mips.c: disassemble MSA instructions
disassemble MIPS SIMD Architecture instructions
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
|
Revision tags: qemu-2.1.1, v2.1.1, RHEL-6.6, qemu-kvm-0.12.1.2-2.445.el6, signed-ppc-for-upstream, qemu-kvm-0.12.1.2-2.444.el6-v2, qemu-kvm-0.12.1.2-2.444.el6, qemu-kvm-0.12.1.2-2.443.el6, qemu-kvm-0.12.1.2-2.442.el6, qemu-guest-agent-2.1.0-3.el7, qemu-kvm-rhev-2.1.0-3.el7, qemu-kvm-1.5.3-60.el7_0.7, qemu-kvm-1.5.3-69.el7, qemu-kvm-0.12.1.2-2.441.el6, vfio-pci-for-qemu-20140825.0, qemu-kvm-0.12.1.2-2.440.el6, qemu-kvm-0.12.1.2-2.439.el6, v2.0.2, qemu-kvm-rhev-2.1.0-2.el7, v2.0.1, qemu-kvm-1.5.3-60.el7_0.6, qemu-kvm-1.5.3-68.el7, qemu-guest-agent-2.1.0-2.el7, qemu-kvm-0.12.1.2-2.438.el6, qemu-kvm-0.12.1.2-2.437.el6, qemu-kvm-1.5.3-67.el7, qemu-kvm-0.12.1.2-2.436.el6, qemu-kvm-0.12.1.2-2.415.el6_5.14, vfio-pci-for-qemu-20140805.0, qemu-kvm-0.12.1.2-2.435.el6, qemu-kvm-0.12.1.2-2.415.el6_5.13, qemu-kvm-rhev-2.1.0-1.el7, qemu-2.1.0, v2.1.0, qemu-kvm-0.12.1.2-2.434.el6, qemu-kvm-0.12.1.2-2.433.el6, qemu-2.1.0-rc5, v2.1.0-rc5, qemu-kvm-0.12.1.2-2.432.el6, v2.1.0-rc4, qemu-kvm-0.12.1.2-2.431.el6, qemu-2.1.0-rc3, v2.1.0-rc3, v1.7.2, qom-devices-for-2.1, qemu-2.1.0-rc2, v2.1.0-rc2, qemu-kvm-1.5.3-66.el7, qemu-kvm-rhev-2.0.0-3.el7ev, qemu-kvm-0.12.1.2-2.430.el6, qemu-2.1.0-rc1, v2.1.0-rc1, qemu-kvm-0.12.1.2-2.415.el6_5.12, prep-for-2.1 |
|
#
9456c2fb |
| 07-Jul-2014 |
Leon Alrae <leon.alrae@imgtec.com> |
target-mips: add TLBINV support
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries w
target-mips: add TLBINV support
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified.
TLBINVF causes all entries to be invalidated.
Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
show more ...
|