Home
last modified time | relevance | path

Searched refs:MIP_MTIP (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h733 #define MIP_MTIP (1 << IRQ_M_TIMER) macro
756 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h56 #define MIP_MTIP BIT(IRQ_M_TIMER) macro
/openbmc/qemu/hw/intc/
H A Driscv_aclint.c297 if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { in riscv_aclint_mtimer_realize()