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Searched refs:MIP_MSIP (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/intc/
H A Driscv_aclint.c417 return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); in riscv_aclint_swi_read()
488 if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) { in riscv_aclint_swi_realize()
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h729 #define MIP_MSIP (1 << IRQ_M_SOFT) macro
756 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h53 #define MIP_MSIP BIT(IRQ_M_SOFT) macro