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Searched refs:MII_BMCR (Results 1 – 25 of 162) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dphy.c60 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
68 val = phy_read(phy, MII_BMCR); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
84 val = gpcs_phy_read(phy, MII_BMCR); in emac_mii_reset_gpcs()
87 gpcs_phy_write(phy, MII_BMCR, val); in emac_mii_reset_gpcs()
92 val = gpcs_phy_read(phy, MII_BMCR); in emac_mii_reset_gpcs()
98 gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_gpcs()
120 ctl = phy_read(phy, MII_BMCR); in genmii_setup_aneg()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
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/openbmc/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88e1xxx.c53 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET); in mv88e1xxx_reset()
56 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_reset()
129 (void) simple_mdio_read(phy, MII_BMCR, &ctl); in mv88e1xxx_set_speed_duplex()
144 (void) simple_mdio_write(phy, MII_BMCR, ctl); in mv88e1xxx_set_speed_duplex()
167 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_autoneg_enable()
170 (void) simple_mdio_write(cphy, MII_BMCR, ctl); in mv88e1xxx_autoneg_enable()
188 (void) simple_mdio_read(cphy, MII_BMCR, &ctl); in mv88e1xxx_autoneg_disable()
190 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART); in mv88e1xxx_autoneg_disable()
196 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART); in mv88e1xxx_autoneg_restart()
235 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK); in mv88e1xxx_set_loopback()
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/openbmc/linux/drivers/net/
H A Dsungem_phy.c72 val = __sungem_phy_read(phy, phy_id, MII_BMCR); in reset_one_mii_phy()
75 __sungem_phy_write(phy, phy_id, MII_BMCR, val); in reset_one_mii_phy()
80 val = __sungem_phy_read(phy, phy_id, MII_BMCR); in reset_one_mii_phy()
86 __sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE); in reset_one_mii_phy()
220 sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN); in bcm5400_suspend()
276 sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN); in bcm5401_suspend()
295 sungem_phy_write(phy, MII_BMCR, BMCR_RESET); in bcm5411_init()
296 sungem_phy_write(phy, MII_BMCR, 0x1340); in bcm5411_init()
334 ctl = sungem_phy_read(phy, MII_BMCR); in genmii_setup_aneg()
336 sungem_phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
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H A Dmii.c79 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_gset()
165 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_get_link_ksettings()
291 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_sset()
293 mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr); in mii_ethtool_sset()
300 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_sset()
313 mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp); in mii_ethtool_sset()
388 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_set_link_ksettings()
390 mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr); in mii_ethtool_set_link_ksettings()
397 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); in mii_ethtool_set_link_ksettings()
411 mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp); in mii_ethtool_set_link_ksettings()
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/openbmc/u-boot/drivers/qe/
H A Duec_phy.c259 ctrl = uec_phy_read(mii_info, MII_BMCR); in genmii_setup_forced()
289 uec_phy_write(mii_info, MII_BMCR, ctrl); in genmii_setup_forced()
297 ctl = uec_phy_read(mii_info, MII_BMCR); in genmii_restart_aneg()
299 uec_phy_write(mii_info, MII_BMCR, ctl); in genmii_restart_aneg()
334 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in marvell_config_aneg()
511 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in uec_marvell_init()
583 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) | in dm9161_init()
586 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) & in dm9161_init()
899 status = uec_phy_read(mii_info, MII_BMCR); in marvell_phy_interface_mode()
900 uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE); in marvell_phy_interface_mode()
/openbmc/linux/drivers/net/phy/
H A Dste10Xp.c35 value = phy_read(phydev, MII_BMCR); in ste10Xp_config_init()
40 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
45 value = phy_read(phydev, MII_BMCR); in ste10Xp_config_init()
H A Dnational.c123 int bmcr = phy_read(phydev, MII_BMCR); in ns_giga_speed_fallback()
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
131 phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN)); in ns_giga_speed_fallback()
H A Ddavicom.c123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
H A Det1011c.c49 int ctl = phy_read(phydev, MII_BMCR); in et1011c_config_aneg()
56 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET); in et1011c_config_aneg()
H A Dax88796b.c37 ret = phy_write(phydev, MII_BMCR, 0); in asix_soft_reset()
62 val = phy_read(phydev, MII_BMCR); in asix_ax88772a_read_status()
H A Dlxt.c199 control = phy_read(phydev, MII_BMCR); in lxt973a2_update_link()
289 val = phy_read(phydev, MII_BMCR); in lxt973_probe()
292 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
/openbmc/u-boot/drivers/net/phy/
H A Dxilinx_phy.c69 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
122 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
124 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); in xilinxphy_config()
H A Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
H A Dphy.c140 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
153 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
163 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
193 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
365 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_parse_link()
809 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { in phy_reset()
822 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
824 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
H A Daquantia.c282 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
290 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
298 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
329 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
378 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_startup()
H A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
H A Dmarvell.c134 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
142 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
510 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
512 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
611 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
613 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()
/openbmc/u-boot/common/
H A Dmiiphyutil.c359 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
363 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { in miiphy_reset()
377 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
425 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_speed()
488 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_duplex()
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c118 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR, in vsc8211_autoneg_enable()
125 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR, in vsc8211_autoneg_restart()
136 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr); in vsc8211_get_link_status()
212 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr); in vsc8211_get_link_status_fiber()
318 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN, in vsc8211_power_down()
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dlxt972.c92 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in lxt972_auto_negotiate()
97 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); in lxt972_auto_negotiate()
/openbmc/linux/drivers/net/dsa/b53/
H A Db53_serdes.c95 reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), in b53_serdes_an_restart()
98 b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR), in b53_serdes_an_restart()
148 reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), in b53_serdes_link_set()
154 b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR), in b53_serdes_link_set()
/openbmc/qemu/hw/net/fsl_etsec/
H A Dmiim.c43 case MII_BMCR: in miim_read_cycle()
80 case MII_BMCR: in miim_write_cycle()
/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunbmac.c501 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); in try_next_permutation()
503 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); in try_next_permutation()
507 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); in try_next_permutation()
515 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); in try_next_permutation()
519 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); in try_next_permutation()
536 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); in bigmac_timer()
590 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); in bigmac_begin_auto_negotiation()
594 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); in bigmac_begin_auto_negotiation()
596 bigmac_tcvr_write(bp, tregs, MII_BMCR, bp->sw_bmcr); in bigmac_begin_auto_negotiation()
600 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, MII_BMCR); in bigmac_begin_auto_negotiation()
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/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-6352.c128 return marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_PDOWN, val); in marvell_c22_pcs_power()
209 err = __mdiodev_modify_changed(&mpcs->mdio, MII_BMCR, BMCR_ANENABLE, in marvell_c22_pcs_config()
230 marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_ANRESTART, BMCR_ANRESTART); in marvell_c22_pcs_an_restart()
246 err = marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_SPEED100 | in marvell_c22_pcs_link_up()
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dphy.c1146 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); in e1000_copper_link_autoneg()
1151 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); in e1000_copper_link_autoneg()
1238 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); in e1000e_phy_force_speed_duplex_igp()
1244 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); in e1000e_phy_force_speed_duplex_igp()
1316 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); in e1000e_phy_force_speed_duplex_m88()
1322 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); in e1000e_phy_force_speed_duplex_m88()
1409 ret_val = e1e_rphy(hw, MII_BMCR, &data); in e1000_phy_force_speed_duplex_ife()
1415 ret_val = e1e_wphy(hw, MII_BMCR, data); in e1000_phy_force_speed_duplex_ife()
2116 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); in e1000e_phy_sw_reset()
2121 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); in e1000e_phy_sw_reset()
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