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Searched refs:MDREFR_E1PIN (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c108 tmp &= ~(MDREFR_APD | MDREFR_E1PIN); in pxa2xx_dram_init()
130 writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR); in pxa2xx_dram_init()
/openbmc/linux/arch/arm/mach-pxa/
H A Dsmemc.h67 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ macro
/openbmc/linux/arch/arm/mach-sa1100/
H A Dsleep.S108 bic r11, r11, #MDREFR_E1PIN
/openbmc/linux/drivers/clk/pxa/
H A Dclk-pxa.c32 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ macro
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1548 #define MDREFR_E1PIN (1 << 20) macro
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2480 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ macro
/openbmc/u-boot/include/
H A DSA-1100.h2053 #define MDREFR_E1PIN (1 << 20) macro