Searched refs:MDREFR (Results 1 – 11 of 11) sorted by relevance
| /openbmc/u-boot/arch/arm/cpu/pxa/ |
| H A D | pxa2xx.c | 103 tmp = readl(MDREFR) & ~0xfff; in pxa2xx_dram_init()
111 writelrb(tmp, MDREFR); in pxa2xx_dram_init()
129 writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR); in pxa2xx_dram_init()
130 writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR); in pxa2xx_dram_init()
173 tmp = readl(MDREFR); in pxa2xx_dram_init()
175 writelrb(tmp, MDREFR); in pxa2xx_dram_init()
281 writel(MDREFR_SLFRSH, MDREFR); in reset_cpu()
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 178 sd->mdrefr = MDREFR & 0xffbffff0; in sdram_calculate_timing()
200 MDREFR = (MDREFR & 0xffff000f) | (dri << 4); in sdram_set_refresh()
201 (void) MDREFR; in sdram_set_refresh()
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| /openbmc/linux/arch/arm/mach-sa1100/ |
| H A D | sleep.S | 36 ldr r6, =MDREFR
124 @ Step 2 clear DRI field in MDREFR
127 @ Step 3 set SLFRSH bit in MDREFR
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| /openbmc/linux/arch/arm/mach-pxa/ |
| H A D | pxa27x.c | 105 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); in pxa27x_cpu_pm_save()
113 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); in pxa27x_cpu_pm_restore()
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| H A D | generic.c | 91 return MDREFR; in pxa_smemc_get_mdrefr()
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| H A D | reset.c | 84 writel_relaxed(MDREFR_SLFRSH, MDREFR); in do_hw_reset()
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| H A D | smemc.h | 16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ macro
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| H A D | sleep.S | 56 ldr r4, =MDREFR
97 ldr r4, =MDREFR
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| /openbmc/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 2287 #define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ macro
2450 #define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ macro
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| /openbmc/u-boot/include/ |
| H A D | SA-1100.h | 2039 #define MDREFR \ macro
2044 #define MDREFR (io_p2v(_MDREFR)) macro
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| /openbmc/linux/arch/arm/mach-sa1100/include/mach/ |
| H A D | SA-1100.h | 1541 #define MDREFR __REG(0xA000001C) macro
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