Searched refs:MC (Results 1 – 25 of 109) sorted by relevance
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19 IPMI MC Reset Warm (run)20 IPMI MC Reset Warm (run) (mfg)21 IPMI MC Reset Warm (off)22 IPMI MC Reset Warm (off) (mfg)23 IPMI MC Reset Cold (off)24 IPMI MC Reset Cold (off) (mfg)25 IPMI MC Reset Cold (run)26 IPMI MC Reset Cold (run) (mfg)27 IPMI Std MC Reset Warm (off)28 IPMI Std MC Reset Warm (off) (mfg)[all …]
41 IPMI MC Reset Warm (run)42 IPMI MC Reset Warm (run) (mfg)43 IPMI MC Reset Warm (off)44 IPMI MC Reset Warm (off) (mfg)45 IPMI MC Reset Cold (off)46 IPMI MC Reset Cold (off) (mfg)47 IPMI MC Reset Cold (run)48 IPMI MC Reset Cold (run) (mfg)49 IPMI Std MC Reset Warm (off)50 IPMI Std MC Reset Warm (off) (mfg)[all …]
21 IPMI MC Reset Warm (run) (mfg)22 IPMI MC Reset Warm (off) (mfg)23 IPMI MC Reset Cold (off) (mfg)24 IPMI MC Reset Cold (run) (mfg)25 IPMI Std MC Reset Warm (off) (mfg)26 IPMI Std MC Reset Warm (run) (mfg)27 IPMI Std MC Reset Cold (off) (mfg)28 IPMI Std MC Reset Cold (run) (mfg)
1 IPMI MC Reset Warm2 IPMI MC Reset Warm (mfg)
56 IPMI MC Reset Warm (run) 0 0 057 IPMI MC Reset Warm (run) (mfg) 0 0 058 IPMI MC Reset Warm (off) 0 0 059 IPMI MC Reset Warm (off) (mfg) 0 0 060 IPMI MC Reset Cold (run) 0 0 061 IPMI MC Reset Cold (run) (mfg) 0 0 062 IPMI MC Reset Cold (off) 0 0 063 IPMI MC Reset Cold (off) (mfg) 0 0 064 IPMI Std MC Reset Warm (run) 0 0 065 IPMI Std MC Reset Warm (run) (mfg) 0 0 0[all …]
30 Sources of abstracted link state information presented by the MC firmware42 | | MC firmware54 | MC firmware polling MAC PCS for link |62 Depending on an MC firmware configuration setting, each MAC may be in one of two modes:65 the MC firmware by polling the MAC PCS. Without the need to register a69 - DPMAC_LINK_TYPE_PHY: The MC firmware is left waiting for link state update93 dpmac_set_link_state() MC firmware API.107 (3) In order to configure the HW MAC, the MC Firmware API132 | MC Firmware |145 (2) The dpni_enable() MC API called on the associated fsl_mc_device.[all …]
22 A DPAA2 hardware component called the Management Complex (or MC) manages the23 DPAA2 hardware resources. The MC provides an object-based abstraction for25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and28 The MC provides memory-mapped I/O command interfaces (MC portals)48 | | Management Complex (MC) | |61 | -MC portals ... |67 The MC mediates operations such as create, discover,70 the MC and are done directly using memory mapped regions in121 A DPRC has a mappable MMIO region (an MC portal) that can be used122 to send MC commands. It has an interrupt for status events (like[all …]
30 Complex (MC) portals. MC abstracts most of these resources as DPAA2 objects32 hardware resources, like queues, do not have a corresponding MC object and60 | MC hardware portals |131 managed by MC and completely transparent to the Ethernet driver.157 A net device is created for each DPNI object probed on the MC bus. Each DPNI has162 added to a container on the MC bus in one of two ways: statically, through a163 Datapath Layout Binary file (DPL) that is parsed by MC at boot time; or created
21 When MC and Debug server is enabled, they carve 512MB away from the high23 with MC and Debug server enabled. Linux only sees 15.5GB.30 | 256MB | MC34 MC requires the memory to be aligned with 512MB, so even debug server is52 | MC FW |54 | MC DPL Blob |79 | MC DPC Blob (1M) | |81 | MC DPL Blob (1M) | |83 | MC FW (4M) | |101 | MC DPC Blob (1M) | |[all …]
48 the MC control register region.53 defining the MC's registers:58 -the second region is the MC control registers. This65 MC address space and the parent system address space.67 The MC address space is defined by 3 components:71 0x0 - MC portals85 the relationship between the Ethernet MACs which belong to the MC142 interrupts for the MC. When there is no translation170 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */171 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */[all …]
2 IPMB Driver for a Satellite MC20 Controller or Satellite MC) via IPMB and the device26 IPMB driver for Satellite MC29 ipmb-dev-int - This is the driver needed on a Satellite MC to35 function to set the Satellite MC as an I2C slave.91 If you have multiple BMCs, each connected to your Satellite MC via99 Satellite MC
14 300, 1300, 1400, 400SC, 500SC, 1500SC, 1550, 600SC, 1600SC, 650, 1655MC,96 1655MC HC_SMITYPE_TYPE2
9 MC - Memory controller35 Required properties for MC subnode:37 - reg : First resource shall be the MC PMU resource.38 - enable-bit-index : The bit indicates if the according MC is enabled.
13 MC bus.39 switch objects discovered on the Freeescale MC bus.
24 Repeat Keyword ${LOOP_COUNT} times IPMI MC Reset Warm (off)31 Repeat Keyword ${LOOP_COUNT} times IPMI MC Reset Cold (run)
507 IPMI MC Reset Warm (run)508 [Documentation] Do "IPMI MC Reset Warm (run)" boot test.529 ... \ loc_boot_stack=IPMI MC Reset Warm (run)534 IPMI MC Reset Warm (off)535 [Documentation] Do "IPMI MC Reset Warm (off)" boot test.556 ... \ loc_boot_stack=IPMI MC Reset Warm (off)561 IPMI MC Reset Cold (run)562 [Documentation] Do "IPMI MC Reset Cold (run)" boot test.583 ... \ loc_boot_stack=IPMI MC Reset Cold (run)588 IPMI MC Reset Cold (off)[all …]
57 #define write_counter(V, MC) writeq(V, MC) argument58 #define read_counter(MC) readq(MC) argument60 #define write_counter(V, MC) writel(V, MC) argument61 #define read_counter(MC) readl(MC) argument
115 - :term:`MC API`;121 MC API129 MC-centric130 :term:`V4L2 Hardware` device driver that requires :term:`MC API`.
9 using the NXP MC bus driver.
100 DPAA2 MC 0x00A00000113 DPAA2 MC 0x00A00000 0x05000120 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined123 - mcmemsize: MC DRAM block size. If this variable is not defined
9 enum enetc_mac_addr_type {UC, MC, MADDR_TYPE}; enumerator
7 - interrupts : Should contain MC General interrupt.
19 bool "Management Complex (MC) userspace support"
2 .. c:namespace:: MC
2 .. c:namespace:: MC.request