1*0760e8faSHiroshi DoyuNVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) 2*0760e8faSHiroshi Doyu 3*0760e8faSHiroshi DoyuRequired properties: 4*0760e8faSHiroshi Doyu- compatible : "nvidia,tegra30-smmu" 5*0760e8faSHiroshi Doyu- reg : Should contain 3 register banks(address and length) for each 6*0760e8faSHiroshi Doyu of the SMMU register blocks. 7*0760e8faSHiroshi Doyu- interrupts : Should contain MC General interrupt. 8*0760e8faSHiroshi Doyu- nvidia,#asids : # of ASIDs 9*0760e8faSHiroshi Doyu- dma-window : IOVA start address and length. 10*0760e8faSHiroshi Doyu- nvidia,ahb : phandle to the ahb bus connected to SMMU. 11*0760e8faSHiroshi Doyu 12*0760e8faSHiroshi DoyuExample: 13*0760e8faSHiroshi Doyu smmu { 14*0760e8faSHiroshi Doyu compatible = "nvidia,tegra30-smmu"; 15*0760e8faSHiroshi Doyu reg = <0x7000f010 0x02c 16*0760e8faSHiroshi Doyu 0x7000f1f0 0x010 17*0760e8faSHiroshi Doyu 0x7000f228 0x05c>; 18*0760e8faSHiroshi Doyu nvidia,#asids = <4>; /* # of ASIDs */ 19*0760e8faSHiroshi Doyu dma-window = <0 0x40000000>; /* IOVA start & length */ 20*0760e8faSHiroshi Doyu nvidia,ahb = <&ahb>; 21*0760e8faSHiroshi Doyu }; 22