| /openbmc/linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | phy.h | 97 (((reg) & MAX_PHY_REG_ADDRESS) |\
99 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
103 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
105 ~MAX_PHY_REG_ADDRESS)))
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| H A D | phy.c | 135 if (offset > MAX_PHY_REG_ADDRESS) { in e1000e_read_phy_reg_mdic()
214 if (offset > MAX_PHY_REG_ADDRESS) { in e1000e_write_phy_reg_mdic()
296 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_read_phy_reg_m88()
321 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_write_phy_reg_m88()
378 MAX_PHY_REG_ADDRESS & offset, in __e1000e_read_phy_reg_igp()
444 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & in __e1000e_write_phy_reg_igp()
2426 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_write_phy_reg_bm()
2484 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_read_phy_reg_bm()
2528 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_read_phy_reg_bm2()
2571 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in e1000e_write_phy_reg_bm2()
[all …]
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| H A D | 80003es2lan.c | 351 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { in e1000_read_phy_reg_gg82563_80003es2lan()
385 MAX_PHY_REG_ADDRESS & offset, in e1000_read_phy_reg_gg82563_80003es2lan()
391 MAX_PHY_REG_ADDRESS & offset, in e1000_read_phy_reg_gg82563_80003es2lan()
420 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { in e1000_write_phy_reg_gg82563_80003es2lan()
454 MAX_PHY_REG_ADDRESS & in e1000_write_phy_reg_gg82563_80003es2lan()
460 MAX_PHY_REG_ADDRESS & in e1000_write_phy_reg_gg82563_80003es2lan()
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| H A D | defines.h | 688 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
770 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
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| H A D | ich8lan.h | 111 ((reg) & MAX_PHY_REG_ADDRESS))
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| /openbmc/qemu/hw/net/ |
| H A D | igb_core.h | 68 uint16_t phy[MAX_PHY_REG_ADDRESS + 1];
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| H A D | e1000_regs.h | 226 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
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| H A D | igb_regs.h | 335 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
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| H A D | igb.c | 576 VMSTATE_UINT16_ARRAY(core.phy, IGBState, MAX_PHY_REG_ADDRESS + 1),
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| H A D | igb_core.c | 2647 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = {
2672 assert(addr <= MAX_PHY_REG_ADDRESS); in igb_phy_reg_write()
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| /openbmc/linux/drivers/net/ethernet/intel/igc/ |
| H A D | igc_phy.c | 554 if (offset > MAX_PHY_REG_ADDRESS) { in igc_read_phy_reg_mdic()
610 if (offset > MAX_PHY_REG_ADDRESS) { in igc_write_phy_reg_mdic()
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| H A D | igc_defines.h | 607 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
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| /openbmc/linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_phy.c | 119 if (offset > MAX_PHY_REG_ADDRESS) { in igb_read_phy_reg_mdic()
175 if (offset > MAX_PHY_REG_ADDRESS) { in igb_write_phy_reg_mdic()
401 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in igb_read_phy_reg_igp()
440 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, in igb_write_phy_reg_igp()
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| H A D | e1000_defines.h | 871 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
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| /openbmc/u-boot/drivers/net/ |
| H A D | e1000.h | 1900 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
2145 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
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| H A D | e1000.c | 4373 if (reg_addr > MAX_PHY_REG_ADDRESS) { in e1000_read_phy_reg()
4451 if (reg_addr > MAX_PHY_REG_ADDRESS) { in e1000_write_phy_reg()
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| /openbmc/linux/drivers/net/ethernet/intel/e1000/ |
| H A D | e1000_hw.c | 2800 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, in e1000_read_phy_reg()
2815 if (reg_addr > MAX_PHY_REG_ADDRESS) { in e1000_read_phy_reg_ex()
2939 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, in e1000_write_phy_reg()
2953 if (reg_addr > MAX_PHY_REG_ADDRESS) { in e1000_write_phy_reg_ex()
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| H A D | e1000_hw.h | 2491 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ macro
2913 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
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