Searched refs:MAX_INTERFACE_NUM (Results 1 – 11 of 11) sorted by relevance
90 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];91 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];92 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];93 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];114 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_reg_dump()121 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()135 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()376 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_print_log()515 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_print_stability_log()520 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_print_stability_log()[all …]
13 u32 nominal_adll[MAX_INTERFACE_NUM * MAX_BUS_NUM];14 enum hws_training_ip_stat train_status[MAX_INTERFACE_NUM];15 u8 result_mat[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];16 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];18 u8 result_all_bit[MAX_BUS_NUM * BUS_WIDTH_IN_BITS * MAX_INTERFACE_NUM];19 u8 max_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];20 u8 min_pbs_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];21 u8 max_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];22 u8 min_adll_per_pup[MAX_INTERFACE_NUM][MAX_BUS_NUM];23 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];[all …]
20 static struct write_supp_result wr_supp_res[MAX_INTERFACE_NUM][MAX_BUS_NUM];44 u32 cs_enable_reg_val[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_dynamic_read_leveling()46 u32 data_read[MAX_INTERFACE_NUM + 1] = { 0 }; in ddr3_tip_dynamic_read_leveling()47 u8 rl_values[MAX_CS_NUM][MAX_BUS_NUM][MAX_INTERFACE_NUM]; in ddr3_tip_dynamic_read_leveling()55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()199 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()267 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()290 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()[all …]
18 u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];19 u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];20 u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];21 u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];22 u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];23 u8 interface_state[MAX_INTERFACE_NUM];24 u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];27 static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];46 u32 data_read[MAX_INTERFACE_NUM] = { 0 }; in ddr3_tip_write_additional_odt_setting()182 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_vref()[all …]
89 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];122 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];156 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);157 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);158 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],160 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],161 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
21 u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);22 u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];23 u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];24 u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];55 enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()59 u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()63 u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS]; in ddr3_tip_centralization()73 u32 cs_enable_reg_val[MAX_INTERFACE_NUM]; in ddr3_tip_centralization()80 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()103 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()[all …]
16 u32 phy_reg_bk[MAX_INTERFACE_NUM][MAX_BUS_NUM][BUS_WIDTH_IN_BITS];18 u32 training_res[MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS *20 u8 byte_status[MAX_INTERFACE_NUM][MAX_BUS_NUM]; /* holds the bit status in the byte in wrapper func…321 [MAX_INTERFACE_NUM * MAX_BUS_NUM * BUS_WIDTH_IN_BITS * search + in ddr3_tip_get_buf_ptr()364 if (interface_num >= MAX_INTERFACE_NUM) { in ddr3_tip_ip_training()706 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_read_training_result()738 if (if_id >= MAX_INTERFACE_NUM) { in ddr3_tip_read_training_result()852 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()857 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_load_all_pattern_to_mem()909 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_load_pattern_to_mem()[all …]
39 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];347 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller()363 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()647 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()1018 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_if_polling()1025 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()1099 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_read_modify_write()1211 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_freq_set()1226 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_freq_set()1234 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()[all …]
78 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_bist_read_result()127 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in hws_ddr3_run_bist()186 struct bist_result st_bist_result[MAX_INTERFACE_NUM]; in ddr3_tip_print_bist_res()190 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()206 for (i = 0; i < MAX_INTERFACE_NUM; i++) { in ddr3_tip_print_bist_res()
10 #define MAX_INTERFACE_NUM 1 macro
1411 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_configure_phy()