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Searched refs:MAKE_64BIT_MASK (Results 1 – 25 of 100) sorted by relevance

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/openbmc/qemu/include/hw/pci-host/
H A Ddino.h89 MAKE_64BIT_MASK(0, 1), /* GMASK */
90 MAKE_64BIT_MASK(0, 7), /* PAMR */
91 MAKE_64BIT_MASK(0, 7), /* PAPR */
92 MAKE_64BIT_MASK(0, 8), /* DAMODE */
93 MAKE_64BIT_MASK(0, 7), /* PCICMD */
94 MAKE_64BIT_MASK(0, 9), /* PCISTS */
95 MAKE_64BIT_MASK(0, 32), /* Undefined */
96 MAKE_64BIT_MASK(0, 8), /* MLTIM */
97 MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */
98 MAKE_64BIT_MASK(0, 24), /* PCIROR */
[all …]
/openbmc/qemu/target/riscv/
H A Dinternals.h96 return f | MAKE_64BIT_MASK(32, 32); in nanbox_s()
107 uint64_t mask = MAKE_64BIT_MASK(32, 32); in check_nanbox_s()
122 return f | MAKE_64BIT_MASK(16, 48); in nanbox_h()
133 uint64_t mask = MAKE_64BIT_MASK(16, 48); in check_nanbox_h()
/openbmc/qemu/hw/arm/
H A Dsmmu-internal.h93 return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz))); in level_page_mask()
100 return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) & in iova_level_offset()
101 MAKE_64BIT_MASK(0, gsz - 3); in iova_level_offset()
/openbmc/qemu/target/arm/tcg/
H A Dpauth_helper.c72 o |= i & MAKE_64BIT_MASK(32, 4); in pac_cell_inv_shuffle()
80 o |= i & MAKE_64BIT_MASK(60, 4); in pac_cell_inv_shuffle()
366 pac ^= MAKE_64BIT_MASK(top_bit - 2, 1); in pauth_addpac()
378 ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1); in pauth_addpac()
379 pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1); in pauth_addpac()
381 ptr &= MAKE_64BIT_MASK(0, bot_bit); in pauth_addpac()
382 pac &= ~(MAKE_64BIT_MASK(55, 1) | MAKE_64BIT_MASK(0, bot_bit)); in pauth_addpac()
384 ext &= MAKE_64BIT_MASK(55, 1); in pauth_addpac()
424 cmp_mask = MAKE_64BIT_MASK(bot_bit, top_bit - bot_bit); in pauth_auth()
425 cmp_mask &= ~MAKE_64BIT_MASK(55, 1); in pauth_auth()
H A Dmve_helper.c98 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; in mve_element_mask()
2099 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
2100 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
2389 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
2466 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17); in do_sqrshl48_d()
2498 return MAKE_64BIT_MASK(0, 48); in do_uqrshl48_d()
2608 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \ in DO_VIDUP_ALL()
2630 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \
2728 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0; in HELPER()
2814 if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
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/openbmc/qemu/target/hppa/
H A Dhelper.c69 reserved = MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4); in cpu_hppa_put_psw()
73 reserved = MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2); in cpu_hppa_put_psw()
H A Dcpu.h312 ? MAKE_64BIT_MASK(0, 62) in gva_offset_mask()
313 : MAKE_64BIT_MASK(0, 32)); in gva_offset_mask()
/openbmc/qemu/hw/gpio/
H A Dpcf8574.c53 s->lastrq = MAKE_64BIT_MASK(0, PORTS_COUNT); in pcf8574_reset()
54 s->input = MAKE_64BIT_MASK(0, PORTS_COUNT); in pcf8574_reset()
55 s->output = MAKE_64BIT_MASK(0, PORTS_COUNT); in pcf8574_reset()
/openbmc/qemu/target/microblaze/
H A Dmmu.h36 #define TLB_EPN_MASK MAKE_64BIT_MASK(10, 64 - 10)
50 #define TLB_RPN_MASK MAKE_64BIT_MASK(10, 64 - 10)
/openbmc/qemu/target/loongarch/
H A Dinternals.h16 #define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
17 #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
H A Dcpu_helper.c73 (address & MAKE_64BIT_MASK(0, tlb_ps)); in loongarch_map_tlb_entry()
174 return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \ in dmw_va2pa()
/openbmc/qemu/hw/display/
H A Dvga-mmio.c59 MAKE_64BIT_MASK(0, size * 8); in vga_mm_read()
68 value & MAKE_64BIT_MASK(0, size * 8)); in vga_mm_write()
/openbmc/qemu/tcg/tci/
H A Dtcg-target-con-str.h11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
/openbmc/qemu/include/hw/fsi/
H A Dfsi.h16 #define BE_GENMASK(hb, lb) MAKE_64BIT_MASK((lb), ((hb) - (lb) + 1))
/openbmc/qemu/target/ppc/
H A Dmmu-book3s-v3.c31 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { in ppc64_v3_get_pate()
/openbmc/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c271 .rsvd = MAKE_64BIT_MASK(5, 64 - 5),
300 .ro = MAKE_64BIT_MASK(27, 64 - 27) },
302 .ro = MAKE_64BIT_MASK(27, 64 - 27),
/openbmc/qemu/hw/nubus/
H A Dmac-nubus-bridge.c24 bus->slot_available_mask = MAKE_64BIT_MASK(MAC_NUBUS_FIRST_SLOT, in mac_nubus_bridge_init()
/openbmc/qemu/hw/rtc/
H A Dxlnx-zynqmp-rtc.c120 .unimp = MAKE_64BIT_MASK(0, 32),
125 .unimp = MAKE_64BIT_MASK(0, 32),
/openbmc/qemu/hw/intc/
H A Dgicv3_internal.h385 #define ITTADDR_MASK MAKE_64BIT_MASK(ITTADDR_SHIFT, ITTADDR_LENGTH)
393 #define pINTID_MASK MAKE_64BIT_MASK(32, 32)
396 #define DEVID_MASK MAKE_64BIT_MASK(32, 32)
/openbmc/qemu/tcg/
H A Doptimize.c1063 s_mask |= MAKE_64BIT_MASK(32, 32); in fold_masks()
1617 uint64_t mask = MAKE_64BIT_MASK(0, op->args[4]); in fold_deposit()
2079 ctx->s_mask = MAKE_64BIT_MASK(width, 64 - width); in fold_qemu_ld()
2081 ctx->z_mask = MAKE_64BIT_MASK(0, width); in fold_qemu_ld()
2475 s_mask |= MAKE_64BIT_MASK(len, 64 - len); in fold_sextract()
2608 ctx->s_mask = MAKE_64BIT_MASK(8, 56); in fold_tcg_ld()
2611 ctx->z_mask = MAKE_64BIT_MASK(0, 8); in fold_tcg_ld()
2612 ctx->s_mask = MAKE_64BIT_MASK(9, 55); in fold_tcg_ld()
2615 ctx->s_mask = MAKE_64BIT_MASK(16, 48); in fold_tcg_ld()
2618 ctx->z_mask = MAKE_64BIT_MASK(0, 16); in fold_tcg_ld()
[all …]
/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c132 pagesize = MAKE_64BIT_MASK(tlb_ps, 1); in invalidate_tlb_entry()
133 mask = MAKE_64BIT_MASK(0, tlb_ps + 1); in invalidate_tlb_entry()
305 address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); in helper_tlbfill()
595 tmp0 += MAKE_64BIT_MASK(ps, 1); in helper_ldpte()
/openbmc/qemu/target/arm/
H A Dcpu64.c87 vq_mask = MAKE_64BIT_MASK(0, max_vq); in arm_cpu_sve_finalize()
131 vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0; in arm_cpu_sve_finalize()
145 vq_mask = MAKE_64BIT_MASK(0, max_vq); in arm_cpu_sve_finalize()
155 vq_mask = MAKE_64BIT_MASK(0, max_vq); in arm_cpu_sve_finalize()
/openbmc/qemu/hw/i386/
H A Dsgx.c83 return (low & MAKE_64BIT_MASK(12, 20)) + in sgx_calc_section_metric()
84 ((high & MAKE_64BIT_MASK(0, 20)) << 32); in sgx_calc_section_metric()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_farith.c.inc111 tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31));
129 tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63));
/openbmc/qemu/accel/tcg/
H A Dldst_atomicity.c.inc774 uint32_t m = MAKE_64BIT_MASK(0, sz);
802 uint64_t m = MAKE_64BIT_MASK(0, sz);
835 /* Like MAKE_64BIT_MASK(0, sz), but larger. */
837 m = int128_make64(MAKE_64BIT_MASK(0, sz));
839 m = int128_make128(-1, MAKE_64BIT_MASK(0, sz - 64));
887 store_atom_insert_al4(pv - 1, (uint32_t)val << 8, MAKE_64BIT_MASK(8, 16));
891 store_atom_insert_al8(pv - 3, (uint64_t)val << 24, MAKE_64BIT_MASK(24, 16));

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