| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight.rst | 401 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}
402 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc
403 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0
404 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]
405 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]
406 Instruction 0 0x8026B550 E3530004 false CMP r3,#4
407 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1
408 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]
409 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c
411 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4]
[all …]
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| /openbmc/qemu/tests/tcg/plugins/ |
| H A D | insn.c | 44 } Instruction; typedef
51 static Instruction * get_insn_record(const char *disas, uint64_t vaddr, Match *m) in get_insn_record()
54 Instruction *record; in get_insn_record()
67 record = g_new0(Instruction, 1); in get_insn_record()
110 Instruction *insn = (Instruction *) udata; in vcpu_insn_matched_exec_before()
181 Instruction *rec = get_insn_record(insn_disas, in vcpu_tb_trans()
224 Instruction *record; in plugin_exit()
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| /openbmc/qemu/target/hexagon/ |
| H A D | insn.h | 27 struct Instruction;
33 struct Instruction { struct
55 typedef struct Instruction Insn; argument
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| H A D | README | 25 *.idef Instruction semantics definition
28 iclass.def Instruction class definitions used to determine
61 Instruction tag A2_add
63 Instruction semantics "{ RdV=RsV+RtV;}"
121 Instruction tag L2_loadw_locked
123 Instruction semantics "{ fEA_REG(RsV); fLOAD_LOCKED(1,4,u,EA,RdV) }"
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | isa-versions.rst | 24 Power5 - PowerPC User Instruction Set Architecture Book I v2.02
27 PPC970 - PowerPC User Instruction Set Architecture Book I v2.01
31 Power4+ - PowerPC User Instruction Set Architecture Book I v2.01
34 Power4 - PowerPC User Instruction Set Architecture Book I v2.00
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| /openbmc/linux/Documentation/virt/kvm/s390/ |
| H A D | s390-pv.rst | 63 Instruction emulation
71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the
74 Instruction data is copied to and from the SIDA when needed. Guest
88 The Secure Instruction Data Area contains instruction storage
89 data. Instruction data, i.e. data being referenced by an instruction
97 Instruction emulation interceptions
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | rel6.decode | 10 # The MIPS32 Instruction Set Reference Manual, Revision 6.06
14 # The MIPS64 Instruction Set Reference Manual, Revision 6.06
|
| H A D | tx79.decode | 7 # Toshiba Appendix B C790-Specific Instruction Set Details
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| /openbmc/linux/Documentation/arch/loongarch/ |
| H A D | introduction.rst | 109 0x8 Bad (Faulting) Instruction Word BADI
180 0x380 Instruction Fetch WatchPoint FWPC
182 0x381 Instruction Fetch WatchPoint FWPS
184 0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1
186 0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2
188 0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3
190 0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4
200 Basic Instruction Set
203 Instruction formats
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| /openbmc/linux/arch/m68k/ifpsp060/ |
| H A D | iskeleton.S | 59 | Instruction exception handler. For a normal exit, the
62 | Unimplemented Integer Instruction stack frame with
85 | Instruction exception handler. If the instruction was a "chk2"
120 | Instruction exception handler isp_unimp(). If the instruction is a 64-bit
123 | Integer Instruction stack frame and branches to this routine.
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| H A D | isp.doc | 35 Integer Instruction" exception vector #61.
108 For example, if the 68060 hardware took a "Unimplemented Integer Instruction"
175 address) take the Unimplemented Integer Instruction exception. When the
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/highway/ |
| H A D | highway_1.2.0.bb | 1 SUMMARY = "Highway is a C++ library for SIMD (Single Instruction, Multiple Data)"
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| /openbmc/qemu/docs/system/openrisc/ |
| H A D | emulation.rst | 9 - ORBIS32 (OpenRISC Basic Instruction Set)
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| /openbmc/qemu/target/ppc/ |
| H A D | insn32.decode | 365 ### Fixed-Point Select Instruction
544 ### Floating-Point Select Instruction
741 ## Vector Bit Manipulation Instruction
755 ## Vector Permute and Formatting Instruction
798 ## Vector Integer Shift Instruction
922 ## Vector Multiply Instruction
1110 ## VSX Vector Load Special Value Instruction
1167 ## VSX Vector Test Least-Significant Bit by Byte Instruction
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | cpu-feature-registers.rst | 115 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
208 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
288 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
332 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
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| H A D | legacy_instructions.rst | 42 Note: Instruction emulation may not be possible in all cases. See
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| /openbmc/qemu/hw/sparc/ |
| H A D | trace-events | 20 int_helper_icache_freeze(void) "Instruction cache: freeze"
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | encode_subinsn.def | 124 DEF_FIELD32("---! !!!! !!!!!!!! EE------ --------",SUBFIELD_B_SLOT1,"B: Slot1 Instruction")
125 DEF_FIELD32("---- ---- -------- EE-!!!!! !!!!!!!!",SUBFIELD_A_SLOT0,"A: Slot0 Instruction")
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| H A D | system.idef | 36 Q6INSN(Y2_icinva,"icinva(Rs32)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",…
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| /openbmc/linux/arch/arc/kernel/ |
| H A D | entry-arcv2.S | 40 VECTOR EV_Extension ; Extn Instruction Exception
121 ; Instruction fetch or Data access, under a single Exception Vector
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| /openbmc/qemu/target/riscv/ |
| H A D | insn32.decode | 2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
124 # *** RV32I Base Instruction Set ***
180 # *** RV64I Base Instruction Set (in addition to RV32I) ***
194 # *** RV128I Base Instruction Set (in addition to RV64I) ***
343 # *** RV32H Base Instruction Set ***
357 # *** RV64H Base Instruction Set ***
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| /openbmc/u-boot/doc/ |
| H A D | README.NDS32 | 27 - Instruction for efficient power management.
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| /openbmc/linux/tools/perf/scripts/python/ |
| H A D | libxed.py | 80 def Instruction(self): member in LibXED
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| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_svinval.c.inc | 2 * RISC-V translation routines for the Svinval Standard Instruction Set.
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| /openbmc/u-boot/board/renesas/MigoR/ |
| H A D | lowlevel_init.S | 32 ! Instruction Cache Invalidate
|