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Searched refs:ISA_MIPS_R1 (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/mips/
H A Dmips-defs.h19 #define ISA_MIPS_R1 0x0000000000000020ULL macro
66 #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1)
H A Dinternal.h386 } else if (env->insn_flags & ISA_MIPS_R1) { in compute_hflags()
/openbmc/qemu/target/mips/tcg/
H A Dmips16e_translate.c.inc561 check_insn(ctx, ISA_MIPS_R1);
794 check_insn(ctx, ISA_MIPS_R1);
938 check_insn(ctx, ISA_MIPS_R1);
959 check_insn(ctx, ISA_MIPS_R1);
1010 check_insn(ctx, ISA_MIPS_R1);
1026 check_insn(ctx, ISA_MIPS_R1);
1031 check_insn(ctx, ISA_MIPS_R1);
H A Dmicromips_translate.c.inc832 check_insn(ctx, ISA_MIPS_R1);
1120 check_insn(ctx, ISA_MIPS_R1);
1147 check_insn(ctx, ISA_MIPS_R1);
1166 check_insn(ctx, ISA_MIPS_R1);
1312 check_insn(ctx, ISA_MIPS_R1);
H A Dtranslate.c5104 check_insn(ctx, ISA_MIPS_R1); in gen_mfc0()
5859 check_insn(ctx, ISA_MIPS_R1); in gen_mtc0()
6611 check_insn(ctx, ISA_MIPS_R1); in gen_dmfc0()
7326 check_insn(ctx, ISA_MIPS_R1); in gen_dmtc0()
8635 check_insn(ctx, ISA_MIPS_R1); in gen_cp0()
8650 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); in gen_cp0()
8685 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); in gen_compute_branch1()
13138 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | in decode_opc_special_legacy()
13151 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); in decode_opc_special_legacy()
13413 check_insn(ctx, ISA_MIPS_R1); in decode_opc_special2_legacy()
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