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Searched refs:ISA_MIPS5 (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dmips-defs.h18 #define ISA_MIPS5 0x0000000000000010ULL macro
61 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
/openbmc/qemu/disas/
H A Dmips.c622 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) macro
625 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
3934 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c14870 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); in decode_opc_legacy()
14884 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); in decode_opc_legacy()