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Searched refs:IMASK (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/arch/sh/kernel/
H A Dhead_32.S59 mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
338 1: .long 0x000000F0 ! IMASK=0xF
340 1: .long 0x500080F0 ! MD=1, RB=0, BL=1, FD=1, IMASK=0xF
/openbmc/linux/arch/powerpc/kernel/
H A Dexceptions-64s.S108 #define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */ macro
166 .ifndef IMASK
167 IMASK=0
434 .if IMASK
460 li r10,IMASK
465 2: andi. r10,r10,IMASK
1634 IMASK=IRQS_DISABLED
1826 IMASK=IRQS_DISABLED
1911 IMASK=IRQS_DISABLED
2221 IMASK=IRQS_DISABLED
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/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dentry.S262 mov k3, k0 ! Calculate IMASK-bits
270 6: or k0, k2 ! Set the IMASK-bits
502 0: .long 0x000080f0 ! FD=1, IMASK=15
/openbmc/qemu/target/arm/
H A Dtrace-events9 arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
/openbmc/qemu/hw/net/fsl_etsec/
H A Detsec.c59 uint32_t imask = etsec->regs[IMASK].value; in etsec_update_irq()
229 case IMASK: in etsec_write()
H A Dregisters.h112 #define IMASK (0x014 / 4) macro
/openbmc/linux/Documentation/arch/sh/
H A Dregister-banks.rst37 - The SR.IMASK interrupt handler makes use of this to set the
/openbmc/qemu/hw/timer/
H A Dsse-timer.c59 FIELD(CNTP_CTL, IMASK, 1, 1)