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Searched refs:ICH_VMCR_EL2_VENG0_SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/intc/
H A Dgicv3_internal.h201 #define ICH_VMCR_EL2_VENG0_SHIFT 0 macro
202 #define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT)
H A Darm_gicv3_cpuif.c666 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_read()
683 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_write()