Searched refs:ICH_MISR_EL2_VGRP0D (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/hw/intc/ | ||
| H A D | gicv3_internal.h | 268 #define ICH_MISR_EL2_VGRP0D (1U << 5) macro |
| H A D | arm_gicv3_cpuif.c | 455 value |= ICH_MISR_EL2_VGRP0D; in maintenance_interrupt_state() |