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Searched refs:HHI_VIID_CLK_DIV (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c28 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
249 hhi_update_bits(HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
262 hhi_update_bits(HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
266 hhi_update_bits(HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h27 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
H A Daxg.h51 #define HHI_VIID_CLK_DIV 0x128 macro
H A Dgxbb.h33 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
H A Dg12a.h54 #define HHI_VIID_CLK_DIV 0x128 macro
H A Dmeson8b.c1439 .offset = HHI_VIID_CLK_DIV,
1455 .offset = HHI_VIID_CLK_DIV,
1471 .offset = HHI_VIID_CLK_DIV,
1501 .offset = HHI_VIID_CLK_DIV,
1531 .offset = HHI_VIID_CLK_DIV,
1561 .offset = HHI_VIID_CLK_DIV,
1591 .offset = HHI_VIID_CLK_DIV,
1747 .offset = HHI_VIID_CLK_DIV,
1778 .offset = HHI_VIID_CLK_DIV,
H A Daxg.c1345 .offset = HHI_VIID_CLK_DIV,
1376 .offset = HHI_VIID_CLK_DIV,
1679 .offset = HHI_VIID_CLK_DIV,
H A Dgxbb.c1922 .offset = HHI_VIID_CLK_DIV,
1953 .offset = HHI_VIID_CLK_DIV,
2288 .offset = HHI_VIID_CLK_DIV,
H A Dg12a.c3188 .offset = HHI_VIID_CLK_DIV,
3219 .offset = HHI_VIID_CLK_DIV,
3554 .offset = HHI_VIID_CLK_DIV,
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h50 #define HHI_VIID_CLK_DIV 0x128 macro
H A Dclock-gx.h32 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c54 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
299 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
317 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
321 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()