Searched refs:HEVC_ENC_CMD_WAIT_GE (Results 1 – 2 of 2) sorted by relevance
474 #define HEVC_ENC_CMD_WAIT_GE 0x00000106 macro
1120 amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE); in uvd_v6_0_enc_ring_emit_pipeline_sync()