Home
last modified time | relevance | path

Searched refs:GICV3_S (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c968 if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) || in icc_gprio_mask()
1390 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1760 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_read()
1805 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_write()
2169 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; in icc_ctlr_el1_read()
2185 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; in icc_ctlr_el1_write()
2253 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
2255 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
2258 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR; in icc_ctlr_el3_write()
2417 cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V | in icc_reset()
H A Darm_gicv3_common.c512 cs->gicr_statusr[GICV3_S] = 0; in arm_gicv3_common_reset_hold()
557 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset_hold()
H A Darm_gicv3_kvm.c703 c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; in arm_gicv3_icc_reset()
/openbmc/qemu/include/hw/intc/
H A Darm_gicv3_common.h116 #define GICV3_S 0 macro