Searched refs:GICD_CTLR (Results 1 – 12 of 12) sorted by relevance
/openbmc/u-boot/arch/arm/cpu/armv7/ |
H A D | virt-v7.c | 112 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, in armv7_init_nonsec() 113 gic_dist_addr + GICD_CTLR); in armv7_init_nonsec()
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/openbmc/u-boot/arch/arm/lib/ |
H A D | gic_64.S | 31 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ 44 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
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/openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/ |
H A D | gic_v3.c | 38 while (readl(gicv3_data.dist_base + GICD_CTLR) & GICD_CTLR_RWP) { in gicv3_gicd_wait_for_rwp() 334 writel(0, dist_base + GICD_CTLR); in gicv3_dist_init() 357 GICD_CTLR_ENABLE_G1, dist_base + GICD_CTLR); in gicv3_dist_init()
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/openbmc/linux/tools/testing/selftests/kvm/include/aarch64/ |
H A D | gic_v3.h | 14 #define GICD_CTLR 0x0000 macro
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/openbmc/u-boot/arch/arm/include/asm/ |
H A D | gic.h | 11 #define GICD_CTLR 0x0000 macro
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/openbmc/linux/arch/arm64/kvm/vgic/ |
H A D | vgic-mmio-v3.c | 71 case GICD_CTLR: in vgic_mmio_read_v3_misc() 111 case GICD_CTLR: { in vgic_mmio_write_v3_misc() 179 case GICD_CTLR: in vgic_mmio_uaccess_write_v3_misc() 625 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
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/openbmc/u-boot/arch/arm/mach-imx/mx7/ |
H A D | psci-mx7.c | 465 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, in gic_resume() 466 gic_dist_addr + GICD_CTLR); in gic_resume()
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/openbmc/linux/include/linux/irqchip/ |
H A D | arm-gic-v3.h | 13 #define GICD_CTLR 0x0000 macro 114 #define GICR_CTLR GICD_CTLR
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/openbmc/qemu/hw/intc/ |
H A D | arm_gicv3_kvm.c | 336 kvm_gicd_access(s, GICD_CTLR, ®, true); in kvm_arm_gicv3_put() 522 kvm_gicd_access(s, GICD_CTLR, ®, false); in kvm_arm_gicv3_get() 883 GICD_CTLR)) { in kvm_arm_gicv3_realize()
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H A D | arm_gicv3_dist.c | 382 case GICD_CTLR: in gicd_readl() 613 case GICD_CTLR: in gicd_writel()
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H A D | gicv3_internal.h | 31 #define GICD_CTLR 0x0000 macro
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/openbmc/linux/drivers/irqchip/ |
H A D | irq-gic-v3.c | 250 while (readl_relaxed(base + GICD_CTLR) & bit) { in gic_do_wait_for_rwp() 922 writel_relaxed(0, base + GICD_CTLR); in gic_dist_init() 959 writel_relaxed(val, base + GICD_CTLR); in gic_dist_init() 1132 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; in gic_dist_security_disabled()
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