Home
last modified time | relevance | path

Searched refs:GATE_PERI0 (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8173-pericfg.c14 #define GATE_PERI0(_id, _name, _parent, _shift) \ macro
51 GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
52 GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
53 GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
54 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
55 GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
56 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
57 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
58 GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
59 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
[all …]
H A Dclk-mt8135.c441 #define GATE_PERI0(_id, _name, _parent, _shift) \ macro
450 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
451 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
452 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
453 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
454 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
455 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
456 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
457 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
458 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
[all …]
H A Dclk-mt7622.c25 #define GATE_PERI0(_id, _name, _parent, _shift) \ macro
351 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
352 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
353 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
354 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
355 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
356 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
357 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
358 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
359 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
[all …]
H A Dclk-mt2701.c817 #define GATE_PERI0(_id, _name, _parent, _shift) \ macro
824 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
825 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
826 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
827 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
828 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
829 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
830 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
831 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
832 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
[all …]
H A Dclk-mt2712.c874 #define GATE_PERI0(_id, _name, _parent, _shift) \ macro
885 GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0),
886 GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1),
887 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2),
888 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3),
889 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4),
890 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5),
891 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6),
892 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7),
893 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8),
[all …]
H A Dclk-mt7629.c57 #define GATE_PERI0(_id, _name, _parent, _shift) \ macro
430 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "pwm_qtr_26m", 2),
431 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "pwm_qtr_26m", 3),
432 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "pwm_qtr_26m", 4),
433 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "pwm_qtr_26m", 5),
434 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "pwm_qtr_26m", 6),
435 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "pwm_qtr_26m", 7),
436 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "pwm_qtr_26m", 8),
437 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "pwm_qtr_26m", 9),
438 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "faxi", 12),
[all …]
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c630 #define GATE_PERI0(_id, _parent, _shift) { \ macro
647 GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
648 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
649 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
650 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
651 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
652 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
653 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
654 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
655 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
[all …]
H A Dclk-mt7629.c454 #define GATE_PERI0(_id, _parent, _shift) { \ macro
471 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
472 GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
473 GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
474 GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
475 GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
476 GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
477 GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
478 GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
479 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
[all …]