Home
last modified time | relevance | path

Searched refs:FSR_AEXC_SHIFT (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h27 #define FSR_AEXC_SHIFT 0 macro
28 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
29 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
30 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
31 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
32 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
H A Dcsr.c673 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); in write_fflags()
699 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) in read_fcsr()
713 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); in write_fcsr()
/openbmc/linux/arch/sparc/math-emu/
H A Dmath_32.c128 #define FSR_AEXC_SHIFT 5UL macro
129 #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
258 fsr |= ((long)eflag << FSR_AEXC_SHIFT); in record_exception()
H A Dmath_64.c88 #define FSR_AEXC_SHIFT 5UL macro
89 #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)
142 fsr |= ((long)eflag << FSR_AEXC_SHIFT); in record_exception()
/openbmc/qemu/target/sparc/
H A Dcpu.h166 #define FSR_AEXC_SHIFT 5 macro
H A Dfop_helper.c81 env->fsr |= cexc << FSR_AEXC_SHIFT; in check_ieee_exceptions()