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Searched refs:FSR_AEXC (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h33 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) macro
H A Dcsr.c673 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); in write_fflags()
713 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); in write_fcsr()