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Searched refs:FSR (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/arch/arm/include/debug/
H A Drenesas-scif.S17 #define FSR 0x08 macro
21 #define FSR 0x14 macro
25 #define FSR 0x10 macro
40 1001: ldrh \rd, [\rx, #FSR]
47 ldrh \rd, [\rx, #FSR]
49 strh \rd, [\rx, #FSR]
53 1001: ldrh \rd, [\rx, #FSR]
/openbmc/linux/arch/arm/mm/
H A Dabort-ev4.S20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
H A Dabort-ev4t.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
H A Dabort-ev5t.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
26 bic r1, r1, #1 << 11 @ clear bits 11 of FSR
H A Dabort-ev5tj.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
H A Dabort-ev6.S22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
H A Dabort-nommu.S18 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
H A Dabort-ev7.S18 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dabort-lv4t.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
25 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
/openbmc/linux/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h128 #define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
157 #define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c))
461 #define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
462 #define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
463 #define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
464 #define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
465 #define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
466 #define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
467 #define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
468 #define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
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/openbmc/qemu/target/xtensa/
H A Dfpu_helper.c107 env->uregs[FSR] = v & 0x00000f80; in HELPER()
127 env->uregs[FSR] = flags << XTENSA_FSR_FLAGS_SHIFT; in HELPER()
H A Dcpu.h106 FSR = 233, enumerator
H A Dtranslate.c6756 .par = (const uint32_t[]){FSR},
6833 .par = (const uint32_t[]){FSR},
/openbmc/linux/arch/arm/
H A DKconfig617 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
621 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc103 { "FSR", 233, 1 },
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc87 { "FSR", 233, 1 },