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Searched refs:FSL_DDR_CS0_CS1_CS2_CS3 (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/fsl/
H A Doptions.c724 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()
730 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()
734 return FSL_DDR_CS0_CS1_CS2_CS3; in auto_bank_intlv()
1208 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; in populate_memctl_options()
1214 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in populate_memctl_options()
1215 case FSL_DDR_CS0_CS1_CS2_CS3: in populate_memctl_options()
H A Dmain.c312 FSL_DDR_CS0_CS1_CS2_CS3) { in __step_assign_addresses()
313 case FSL_DDR_CS0_CS1_CS2_CS3: in __step_assign_addresses()
H A Dutil.c306 case FSL_DDR_CS0_CS1_CS2_CS3: in print_ddr_info()
H A Dctrl_regs.c2441 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()
2442 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()
2467 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()
2468 case FSL_DDR_CS0_CS1_CS2_CS3: in compute_fsl_memctl_config_regs()
/openbmc/u-boot/include/
H A Dfsl_ddr_sdram.h86 #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) macro