Home
last modified time | relevance | path

Searched refs:FIELD_DP64 (Results 1 – 21 of 21) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c163 t = FIELD_DP64(t, ID_AA64PFR0, RME, value); in cpu_arm_set_rme()
1110 t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); in aarch64_max_tcg_initfn()
1111 t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); in aarch64_max_tcg_initfn()
1112 t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); in aarch64_max_tcg_initfn()
1113 t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); in aarch64_max_tcg_initfn()
1114 t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); in aarch64_max_tcg_initfn()
1132 t = FIELD_DP64(t, CTR_EL0, IDC, 1); in aarch64_max_tcg_initfn()
1133 t = FIELD_DP64(t, CTR_EL0, DIC, 1); in aarch64_max_tcg_initfn()
1137 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ in aarch64_max_tcg_initfn()
1138 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ in aarch64_max_tcg_initfn()
[all …]
/openbmc/qemu/target/loongarch/
H A Dcpu.c183 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); in loongarch_cpu_do_interrupt()
184 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); in loongarch_cpu_do_interrupt()
188 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); in loongarch_cpu_do_interrupt()
193 env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); in loongarch_cpu_do_interrupt()
234 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV, in loongarch_cpu_do_interrupt()
237 env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE, in loongarch_cpu_do_interrupt()
240 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); in loongarch_cpu_do_interrupt()
241 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); in loongarch_cpu_do_interrupt()
242 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, in loongarch_cpu_do_interrupt()
245 env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, in loongarch_cpu_do_interrupt()
[all …]
/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c69 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 1); in raise_mmu_exception()
102 env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64, in raise_mmu_exception()
105 env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32, in raise_mmu_exception()
196 tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); in fill_tlb_entry()
199 tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); in fill_tlb_entry()
200 tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); in fill_tlb_entry()
202 tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); in fill_tlb_entry()
228 env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX, index); in helper_tlbsrch()
229 env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0); in helper_tlbsrch()
233 env->CSR_TLBIDX = FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1); in helper_tlbsrch()
[all …]
H A Dop_helper.c113 env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); in helper_ertn()
114 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0); in helper_ertn()
115 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1); in helper_ertn()
127 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv); in helper_ertn()
128 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie); in helper_ertn()
H A Dconstant_timer.c60 env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); in loongarch_constant_timer_cb()
/openbmc/qemu/target/arm/
H A Dhyp_gdbstub.c144 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); in insert_hw_watchpoint()
148 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); in insert_hw_watchpoint()
152 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); in insert_hw_watchpoint()
156 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); in insert_hw_watchpoint()
174 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); in insert_hw_watchpoint()
175 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); in insert_hw_watchpoint()
H A Dcpu64.c299 t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); in cpu_arm_set_sve()
354 t = FIELD_DP64(t, ID_AA64PFR1, SME, value); in cpu_arm_set_sme()
371 t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); in cpu_arm_set_sme_fa64()
494 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); in arm_cpu_pauth_finalize()
495 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); in arm_cpu_pauth_finalize()
496 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); in arm_cpu_pauth_finalize()
497 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); in arm_cpu_pauth_finalize()
500 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); in arm_cpu_pauth_finalize()
501 isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); in arm_cpu_pauth_finalize()
530 isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); in arm_cpu_pauth_finalize()
[all …]
H A Dcpu.c279 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
283 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
290 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
294 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], in arm_cpu_reset_hold()
345 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
347 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, in arm_cpu_reset_hold()
2104 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); in arm_cpu_realizefn()
2136 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); in arm_cpu_realizefn()
2140 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); in arm_cpu_realizefn()
2181 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); in arm_cpu_realizefn()
[all …]
H A Dcpu.h3198 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
H A Dhelper.c7501 env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, in gpccr_reset()
/openbmc/qemu/hw/cxl/
H A Dcxl-device-utils.c87 bg_status_reg = FIELD_DP64(0, CXL_DEV_BG_CMD_STS, OP, in mailbox_reg_read()
89 bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS, in mailbox_reg_read()
91 bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS, in mailbox_reg_read()
99 status_reg = FIELD_DP64(status_reg, CXL_DEV_MAILBOX_STS, BG_OP, in mailbox_reg_read()
212 status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, BG_OP, in mailbox_reg_write()
214 status_reg = FIELD_DP64(status_reg, CXL_DEV_MAILBOX_STS, ERRNO, rc); in mailbox_reg_write()
216 command_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_CMD, COMMAND_SET, cmd_set); in mailbox_reg_write()
217 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, in mailbox_reg_write()
219 command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD, in mailbox_reg_write()
379 memdev_status_reg = FIELD_DP64(0, CXL_MEM_DEV_STS, MEDIA_STATUS, 1); in memdev_reg_init_common()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_its.c227 itel = FIELD_DP64(itel, ITE_L, VALID, 1); in update_ite()
228 itel = FIELD_DP64(itel, ITE_L, INTTYPE, ite->inttype); in update_ite()
229 itel = FIELD_DP64(itel, ITE_L, INTID, ite->intid); in update_ite()
230 itel = FIELD_DP64(itel, ITE_L, ICID, ite->icid); in update_ite()
231 itel = FIELD_DP64(itel, ITE_L, VPEID, ite->vpeid); in update_ite()
743 cteval = FIELD_DP64(cteval, CTE, VALID, 1); in update_cte()
744 cteval = FIELD_DP64(cteval, CTE, RDBASE, cte->rdbase); in update_cte()
804 dteval = FIELD_DP64(dteval, DTE, VALID, 1); in update_dte()
805 dteval = FIELD_DP64(dteval, DTE, SIZE, dte->size); in update_dte()
806 dteval = FIELD_DP64(dteval, DTE, ITTADDR, dte->ittaddr); in update_dte()
[all …]
H A Darm_gicv3_redist.c317 newval = FIELD_DP64(newval, GICR_VPENDBASER, PENDINGLAST, pendinglast); in gicr_write_vpendbaser()
/openbmc/qemu/hw/sd/
H A Dsdhci.c84 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); in sdhci_check_capareg()
88 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); in sdhci_check_capareg()
92 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); in sdhci_check_capareg()
98 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); in sdhci_check_capareg()
106 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); in sdhci_check_capareg()
112 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); in sdhci_check_capareg()
116 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); in sdhci_check_capareg()
120 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); in sdhci_check_capareg()
124 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); in sdhci_check_capareg()
128 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); in sdhci_check_capareg()
[all …]
/openbmc/qemu/linux-user/aarch64/
H A Dtarget_prctl.h89 FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); in do_prctl_sme_set_vl()
100 env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0); in do_prctl_sme_set_vl()
H A Dsignal.c339 *svcr = FIELD_DP64(*svcr, SVCR, SM, sm); in target_restore_sve_record()
395 *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1); in target_restore_za_record()
/openbmc/qemu/hw/watchdog/
H A Dspapr_watchdog.c181 args[0] = FIELD_DP64(0, PSERIES_WDTQ, MIN_TIMEOUT, WDT_MIN_TIMEOUT); in h_watchdog()
182 args[0] = FIELD_DP64(args[0], PSERIES_WDTQ, NUM, in h_watchdog()
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-trng.c519 value = FIELD_DP64(value, CTRL, PERSODISABLE, 0); in trng_register_write()
520 value = FIELD_DP64(value, CTRL, SINGLEGENMODE, 0); in trng_register_write()
530 value = FIELD_DP64(value, CTRL, EATAU, 0); in trng_register_write()
531 value = FIELD_DP64(value, CTRL, QERTUEN, 0); in trng_register_write()
/openbmc/qemu/include/hw/
H A Dregisterfields.h109 #define FIELD_DP64(storage, reg, field, val) ({ \ macro
155 (regs)[R_ ## reg] = FIELD_DP64((regs)[R_ ## reg], reg, field, val);
/openbmc/qemu/include/hw/cxl/
H A Dcxl_device.h406 dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS, in __toggle_media()
/openbmc/qemu/target/ppc/
H A Dfpu_helper.c459 env->fpscr = FIELD_DP64(env->fpscr, FPSCR, FI, in do_float_check_status()