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Searched refs:ESDCTL_DDR2_EMR3 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/arm1136/mx35/
H A Dmx35_sdram.c13 #define ESDCTL_DDR2_EMR3 0x06000000 macro
90 writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ in mx3_setup_sdram_bank()
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dmx35pdk.h34 #define ESDCTL_DDR2_EMR3 0x06000000 macro
H A Dlowlevel_init.S185 ldr r4, =ESDCTL_DDR2_EMR3